Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's

Observation of oxide breakdown and its effects on the characteristics of ultra-thin-oxide nMOSFET's

“…One possibility is the stronger electric fields in the source/drain overlap region relative to the channel. Classically, the oxide field is approximately constant between the channel and overlap regions; however, for direct tunnel gate oxides, the strong quantum mechanical effects reduce the oxide electric field in the channel relative to the overlap regions [13], [14]. The thinner the oxide, the larger the difference in the field between the overlap regions and the channel [13].…”

Tinkering with the well-tempered MOSFET: source–channel barrier modulation with high-permittivity dielectrics

“…Like drain-induced barrier lowering (DIBL), FIBL couples the drain voltage to the channel, but in this case the path of control, shown by the field lines, lies through the insulator that now has a much larger permittivity than the semiconductor. The two-dimensional coupling depends on the aspect ratio of the insulator thickness to gate length [5,15]. At these gate lengths, the gate still controls the channel with a Ta 2 O 5 insulator (Fig.…”

Surface Chemical Reaction on HfO2Thin Film Etched by High Density Plasma

“…However, new gate oxide candidates must satisfy a standard complementary metal semiconductor (CMOS) processing procedure. For this purpose, an understanding of the relations between the etch characteristics of HfO 2 thin film and the plasma properties is required to develop the low damaged removal process [1][2][3][4][5][6][7][8]. In addition, it is very important to achieve a high etch rate and high selectivity of HfO 2 for the sake of the throughput and reliability of the MIM capacitor.…”