Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters

Cho, Thomas B.; Cline, D.W.; Conroy, C.; Gray, P.R.

doi:10.1007/978-1-4757-2353-3_3

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…To sum up, the interval ∆t is necessary but should be as small as possible. Due to this ∆t, a new frequency limitation is imposed on the input signal, which can be given by [3]…”

Section: Proposed Adc Architecturementioning

confidence: 99%

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A 13-bit, 8 MSample/s pipeline A/D converter

Guo¹,

Li²,

Zhang³

et al. 2009

J. Semicond.

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A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm2, including I/O pads.

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“…To sum up, the interval ∆t is necessary but should be as small as possible. Due to this ∆t, a new frequency limitation is imposed on the input signal, which can be given by [3]…”

Section: Proposed Adc Architecturementioning

confidence: 99%

“…In a typical pipeline ADC, the front-end sample-and-hold amplifier is often removed for low power [2,3] . But in this case, the first pipeline stage has to sample the input signal directly, and the clock skew between the sampling circuit and the comparator circuit will inevitably induce a new frequency limitation of the input signal.…”

Section: Introductionmentioning

confidence: 99%

A 13-bit, 8 MSample/s pipeline A/D converter

Guo¹,

Li²,

Zhang³

et al. 2009

J. Semicond.

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show abstract

“…The degradation of the SNR could be compensated by using larger sample capacitors at a cost of the bandwidth or the power consumption. Figure 4 shows the schematic of the comparator used in the sub-ADC design [4]. Dynamic latched-type comparators are used because of their high speed and zero static power.…”

Section: Speed Analysismentioning

confidence: 99%

A CMOS current-mode pipeline ADC using zero-voltage sampling technique

Hui

Luong²

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

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A low-voltage low-power CMOS current-mode pipeline ADC is presented. Zero-voltage sampling technique and regulated cascode circuits are combined in the sampleand-hold circuits to irlcrease the resolution. Dynamic latched-type comparatclrs are used to implement highspeed low-power sub-ADGs. The multiplying DAC and the comparators are used with a digital error correction (DEC) circuit to realize a low-voltage low-power current-mode pipeline 4DC. Simulation shows that the ADC can work at 20MHz with an 8-bit resolution. The power consumption is '22mW.

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“…Controlled by between input signal and the reference. To reduce the signal Ctrl3, the third and the fourth CA each consists settling time, cascoding more low-gain stages is better of 32 comparators and can give 7-bit resolution together than using fewer high-gain stages [10]. It is very hard to combined with the first and the second CA.…”

mentioning

confidence: 99%

An Adaptive Analog-to-Digital Converter Based on Low-Power Dynamic Latch Comparator

Huang

Zhong

2005 IEEE International Conference on Electro Information Technology

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Benefiting from a small system size and internal This paper presents a low power adaptive flash interconnect, the mixed-signal SoC can provide high AID converter, which enables the dynamic trade-off performance and more functionality at relatively low between resolution and power consumption. Instead of cost. Another advantage of mixed-signal SoC is its using the traditional amplifier-chain type comparators, potential for integrated power management. While the the dynamic latch comparators are applied in order to SoC solution is very attractive, there are many achieve low power dissipation. Furthermore, the non-challenges in such design. One of them is the collapsing OP Amp architecture provides the design with ability to of system design and circuit design into one integrated be fully compatible with standard digital VLSI process. design process. Instead of designing with ICs, the Lower supply voltage and less mask steps is hence system designers needs to design with modules that will achievable. The AID converter was designed with 0.5-be implemented on silicon. Reducing cost, time and risk pm CMOS technology and capable of operating up to of SoC designs requires the re-use of virtual 250 MHz with 5-bit, 6-bit and 7-bit precision.components. This is difficult for analog parts because Benefting from 50% less power consumption than analog building blocks are often different from one application to the other and they have to be retargeted conventional designs and exponentially reduced power addsge o ahpoes[] with linearly reduced resolution, the design IS addsge o ahpoes[] apphliceablet wreluess aplctions the andevrios l Analog to digital converter (ADC) is the key to mixed signal SOCs in that it provides the interface power portable devices.

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Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters

Cited by 8 publications

References 6 publications

A 13-bit, 8 MSample/s pipeline A/D converter

A 13-bit, 8 MSample/s pipeline A/D converter

A CMOS current-mode pipeline ADC using zero-voltage sampling technique

An Adaptive Analog-to-Digital Converter Based on Low-Power Dynamic Latch Comparator

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