In this work we have developed a completely new and novel SAT solver architecture to address three fundamental hurdles blocking the way to a wider application of reconfigurablehardware-based acceleration of SAT, namely, (1) the time overhead of compiling the instance-specific circuit to hardware, (2) the limited sophistication of the hardware algorithm, and (3) the slow clock speeds. The main enabling idea in our work is to implement the communication between literals and clauses by means of a time-multiplexed pipelined bus architecture rather than hardwiring it using on-FPGA routing resources. This allows the circuits for different instances of the SAT problem to be identical except for small local differences. Thus, the incremental synthesis and place-and-route effort required for each instance of the problem becomes negligible compared to the time to actually solve the SAT problem. Interestingly, the time multiplexing feature also allows us to incorporate the dynamic addition of clauses into the SAT solver algorithm given that the compilation/configuration time is negligible. Finally, since the proposed architecture is highly pipelined with very few long wires and no wires crossing FPGA boundaries, high clock speeds are possible. We present the overall architecture and detailed circuits from it in this paper. We also present experimental results showing the performance of the architecture relative to earlier efforts on hardware acceleration of SAT and relative to software implementations.
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