Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs

Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness

“…Several previous studies found that Tch should be less than 2/3 of the gate length (Lg) to suppress SCEs [5][6][7], and recent ITRS recommend using a similar Tch/Lg ratio for future generations of MOSFETs [8]. Recent studies indicate that Tch should be smaller than 1/2 of Lg to suppress SCEs [9]. It is well known that the short-channel performance is degraded when Tch exceeds some critical value.…”

A charge-based compact model for predicting the current–voltage and capacitance–voltage characteristics of heavily doped cylindrical surrounding-gate MOSFETs

“…By surrounding the channel with the gate completely, excellent gate control is achieved to suppress short-channel effects (SCE) [1][2][3]. To study the performance of SRG MOSFETs in actual circuits, an analytical model of SRG MOSFETs is required.…”

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

“…For example, nanowire devices, especially in Gate-All-Around (GAA) architecture, have emerged as the front-runner for pushing Complementary Metal-Oxide-Semiconductor (CMOS) scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts and other contenders, which make them feasible as an option for 15 nm and beyond technology nodes with sub-10 nm channel length devices already demonstrated through simulations [1] and experiments [2]. Indeed, the cylindrical geometry gives inverse logarithmic dependence of the gate capacitance on the channel diameter, and thus the gate length in these devices can be scaled with wire diameter without reducing the gate dielectric thickness aggressively.…”