Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops

Schrape, Oliver; Andjelković, Marko; Breitenreiter, Anselm; Balashov, Alexey; Krstić, Miloš

doi:10.1109/dsd51259.2020.00101

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…Baseline flip-flops are implemented as standard cell gates in IHP's 130 nm technology and compared to the available standard D-flip-flop which is present in the unhardened standard cell library. As published in [65], a TSPC flip-flop candidate is nearly twice as fast as the reference D-flip-flop and saves 41 % of the silicon area.…”

Section: B Tspc-tmr Flip-flopmentioning

confidence: 99%

“…Finally, the output signal needs to be negated by an output inverter. As published in [65], the TSPC-TMR arrangement requires only 130 ps more than a single standard reference D-flip-flop under worst case condition, based on post layout extracted propagation delays. Finally, a normalized overhead of only 5.8 for the area, 7.4 for the energy, and a slight improvement in terms of propagation delay t pg of 0.9 can be obtained in comparison to the baseline, unhardened standard D-flip-flop DFF_STD (see Table I).…”

Section: B Tspc-tmr Flip-flopmentioning

confidence: 99%

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Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Schrape

Andjelković

Breitenreiter

et al. 2021

IEEE Trans. Circuits Syst. I

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Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard nonrad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130 nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV• cm 2 mg ) to (62.5 MeV• cm 2 mg ), depending on the variant.

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Section: B Tspc-tmr Flip-flopmentioning

confidence: 99%

Section: B Tspc-tmr Flip-flopmentioning

confidence: 99%