Design Challenges for 3 Dimensional Network-on-Chip (NoC)

Ashokkumar, N.; Nagarajan, P.; Selvaperumal, SathishKumar; Venkatramana, P.

doi:10.1007/978-3-030-34515-0_82

Cited by 12 publications

(2 citation statements)

References 7 publications

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“…Of the three, memory-based implementations are gaining popularity due to the significant growth of VLSI memory technology.Semiconductor memory is becoming cheaper, faster and consumes less power due to continuous improvements in silicon scaling technology. Advances in memory technology [14][15][16][17][18] have enabled better memory design based on application requirements today, and efficient memory-based multipliers are also possible.In the past, memory was a separate part of the processor unit, but now memory is part of the processor [19][20][21][22]. Since OMS-based multipliers already exist, I wanted to try an efficient OMS-based multiplier design that I hadn't explored and dealt with before.…”

Section: Introductionmentioning

confidence: 99%

Modified Efficient OMS LUT Design for Memory-Based Multiplication

Manikandan¹

2022

JAIMLNN

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This paper proposes an efficient LUT (Look-Up-Table) design called Efficient EOMS (Efficient-OMS Design) for memory-based operations. This proposed design can be used for FPGA implementation as well as ASIC. The proposed design is a better choice than ordinary OMS (Odd Multiplier Store) and is preferred in many DSP calculations where one of the inputs to the filter coefficients is fixed. In this design (N+1), the possible product terms of the input multiplicands with fixed coefficients are stored directly in memory. Doing so allows for a simpler and faster design, unlike the previous proposal OMS (Odd Multiple Storage).Designs that extract odd multiples of the product term can significantly reduce path delay and area complexity with very simple control circuitry. Using (N+1) technology can significantly reduce the area compared to ordinary OMS technology. Additionally, the EOMS technical design is coded in Verilog and simulated and synthesized using Xilinx tools.

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Section: Introductionmentioning

confidence: 99%

Modified Efficient OMS LUT Design for Memory-Based Multiplication

Manikandan¹

2022

JAIMLNN

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“…The 3D integration provides large bandwidth, small foot print, reduced form factor and lower interconnect complexity over the two dimensional integration technologies. [9][10][11] The 3D technology attracted the semiconductor design engineers as it offers tremendous platform to attain more than Moore law. This brings heterogeneous materials such as Silicon (Si), II-V semiconductor and graphene, and technologies such as memories, optoelectronics, and logics on single chip.…”

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confidence: 99%

Analysis of Crosstalk Effects for Ternary Logic MWCNT Bundled Through Silicon Vias

Basha¹,

Venkatramana²

2023

ECS J. Solid State Sci. Technol.

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We present a technique to improve the crosstalk effects in ternary coupled through silicon vias (TSVs). The effects of crosstalk were investigated in TSVs using multi-walled carbon nanotube (MWCNT) as metallic liner and polymers such as polyimide, polypropylene carbonate, and benzocyclobutene (BCB) as dielectric liners. The circuit model for coupled TSVs driven by a ternary inverter was utilized to analyze the various crosstalk issues. The HSPICE tool was utilized to develop the proposed TSVs. The crosstalk issues for the MWCNT TSVs were investigated and compared to single-walled CNT (SWCNT) TSVs. Moreover, the power, power delay product, and energy delay product were analyzed and compared to SWCNT TSVs. All of the performances were also studied for different TSV pitches. The coupled TSVs with BCB showed high performance for the large pitch values. Moreover, it was noted that the coupled TSVs with BCB at 5000μm TSV pitch improved the performance up to 40.03% over the SWCNT TSVs.

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