Design Automation for Digital Systems

“…Since these constraints are expressed as inequalities that specify ranges for constraints, the timing design becomes more difficult as the complexity of the specifications for the V L S I chip increases. 3 Timing design is different from timiilg analysis or circuit simulation. In timing analysis, we assume that all input signals are given a s test patterns and we analyze all the output signal timings.…”

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An expert system to automate timing design

Kara

Rastogi²,

Kawamura

1988

IEEE Des. Test. Comput.

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The authors present a new approach for automating the timing design of interfaces between VLSI chips in microcomputer systems. The Prolog-based expert system, called TDS (for timing design system), incorporates the heuristic knowledge of the hardware designer. TDS is a rule-based system that interprets the specification sheets of VLSI chips and can synthesize, diagnose, and verify timing charts at the expert's level. This approach is unique in that the system uses a functional model based on timing specifications, not the structural information. TDS can also model other interfaces that are based on timing specifications, such as standard bus interfaces.he advent of microprocessors h a s forced many designers to work at the system level, and software is becoming increasingly important in digital system design. Over

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On behavior fault modeling for digital designs

Ghosh

Chakraborty

1991

J Electron Test

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A critical aspect of digital electronics is the testing of the manufactured designs for correct functionality. The testing process consists of first generating a set of test vectors, then applying them as stimuli to the manufactured designs, and finally comparing the output response with that of the desired response. A design is considered acceptable when the output response matches the desired response and is rejected otherwise. Fundamental to the process of test vector generation is the assumption of an underlying fault model that is a model of the failures introduced during manufacture. The choice of the fault model influences the accuracy of testing and the computer CPU time required to generate test vectors for a given design. The most popular fault model in the industry today is the single stuck-at fault at the gate level that requires exorbitantly large CPU times for moderately complex digital designs. This article introduces new high-level behavior fault models that are associated with high-level hardware descriptions of digital designs. The derivation of these faults is based on the failure modes of the language constructs of the high-level hardware description language. Behavior faults include multiple input stuck-at faults and this article also reasons the nature of test vectors for such faults. The potential advantages of behavior fault modeling include early estimates of fault coverage in the design process prior to the synthesis of the gate-level representation of the design, faster fault simulation, and results that may be more comprehensible to the high-level architects. The behavior-fault-modeling approach is evaluated through a study of correlation of the results of behavior fault simulation of several representative digital designs with the results of gate-level single stuck-at fault simulation of equivalent gate-level representations.

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Design Automation for Digital Systems

Cited by 16 publications

References 49 publications

A review of fault models for lsi/vlsi devices

A review of fault models for lsi/vlsi devices

An expert system to automate timing design

On behavior fault modeling for digital designs

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