Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

Structural design guideline to minimize extreme low-k delamination potential in 40nm flip-chip packages

“…In addition to solder joint integrity under temperature cycling (e.g., [1]), delamination in the low-k ILD [2][3][4][5][6][7][8], depicted in Fig. 2, under thermal processes and subsequent reliability tests also becomes a significant reliability issue.…”

“…3. This reliability issue has been properly dealt with through careful selection of the underfill [3,5,6,8]. The rule of thumb is to determine a tradeoff in the modulus and glass transition temperature (T g ) of the underfill so that both solder joints and low-k ILD are reasonably protected.…”