Design and VLSI Implementation of Pipelined Multiply Accumulate Unit

Shanthala, S; Raj, Cyril Prasanna; Kulkarni, S. Y.

doi:10.1109/icetet.2009.72

Cited by 18 publications

(6 citation statements)

References 5 publications

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“…Tab. 2 reveals that the architectures in [12,33,34] consume considerably higher static and average power (in mW) than the proposed SFMAC architecture. The architectures in [35,36] are examined for 16-bit operations at 1 V and 8-bit operations at 1.8 V in 90 and 180 nm technologies.…”

Section: Esc Blockmentioning

confidence: 95%

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872) 10 to + (7.96872) 10 . The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as "block enabling" and "clock gating" are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

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Section: Esc Blockmentioning

confidence: 95%

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

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“…In addition, uses of Radix-4 BM system speed up the process as count of partial products are less in number. [9] Discussed the comparison of multipliers based on different parameters for multiplication algorithms and concluded that the Speed of Wallace tree multiplier is relatively more with medium space utilization, power consumption, and expenditure involved. Dadda Multiplier has high speed with average cost and medium complexity and Area.…”

Section: Multipliersmentioning

confidence: 99%

Applications of Vedic multiplier - A Review

Khubnani¹,

Sharma²,

Subramanyam³

2022

J. Phys.: Conf. Ser.

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Vedic Multiplier is a key tool in rapidly growing technology especially in the immense domain of Image processing, Digital Signal Processing, real-time signal. Multipliers are important block in digital systems and play a critical role in digital designs. Along with accuracy demand for minimizing time area, power, and delay of the processor by enhancing speed is the focus point. Vedic mathematics rules and Algorithms generate partial products concurrently and save time. This paper is a review of the application and modification of Vedic multiplier in different fields and a comparison of Vedic multiplier with other multipliers for enhancing performance parameters.

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“…Also, it suffers some problems such as, high power dissipation, large number of transistors/area, long delay time, power consumption high. The second common approach is the Pass Transistor Logic (PTL), it is popular as CMOS approach, its features as decreased silicon area, speed, reduced power consumption, slower at reduced power, signi cant power dissipation [25][26][27][28].…”

Section: Low Power Vlsi Approaches Overviewmentioning

confidence: 99%

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

El‐Bendary

El-Badry

2021

Preprint

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Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (7, 4) and (11, 7) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No.Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

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Design and VLSI Implementation of Pipelined Multiply Accumulate Unit

Cited by 18 publications

References 5 publications

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Applications of Vedic multiplier - A Review

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

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