Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks

Niazmand, Behrad; Azad, Siavoosh Payandeh; Jervan, Gert; Sepúlveda, Johanna

doi:10.1109/dsd.2019.00108

Cited by 2 publications

(4 citation statements)

References 17 publications

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“…The first one is a baseline cache, which is an opensource parameterizable hardware core [19]. The configuration parameters of the cache include: i) associativity, either fully associative, direct-mapped or set-associative; ii) number of ways per cache set; iii) number of cache lines; and iv) other parameters related to memory and processor address size [20]. The second architecture is a secure cache, a protected version of [19] which was proposed in [20].…”

Section: A Required Inputs For Cache Template Developmentmentioning

confidence: 99%

“…These monitors can be integrated in an invasive or non-invasive (without modifying the cache architecture) way. The target cache architectures described in [19] and [20] allow access of the internal signals of the cache, as shown in Fig. 4.…”

Section: B Integrationmentioning

confidence: 99%

“…LiD-CAT is modelled in Verilog and integrated into two cache designs: i) a baseline cache [19]; and ii) a secure cache, which is the protected version of [19] against accessbased cache attack [20]. The goal is to evaluate its detection accuracy (i.e., both false and true positives) and hardware overhead.…”

Section: A Setupmentioning

confidence: 99%

“…For the secure cache, the false positive results are typically lower and the worst case reaches 11% for mcf. The main reason is due to the protection mechanism of the secure cache of [20]. It masks the accesses in the cache by using random addresses, thus changing the access behavior of Gzip.…”

Section: B Detectors Accuracymentioning

confidence: 99%

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LiD-CAT: A Lightweight Detector for Cache ATtacks

Reinbrecht

Hamdioui

Taouil

et al. 2020

2020 IEEE European Test Symposium (ETS)

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Cache attacks are one of the most widespread and dangerous threats to embedded computing systems' security. A promising approach to detect such attacks at runtime is to monitor the System-on-Chip (SoC) behavior. However, designing a secure SoC capable of detecting such attacks is very challenging: the monitors should be lightweight in order to avoid excessive power/energy and area costs and the attack behavior should be clearly known upfront. In this work, we present LiD-CAT, a lightweight and flexible hardware detector that is aware of leakage patterns that can be used by attackers to perform cache based attacks. LiD-CAT is a cache wrapper that implements a set of leakage properties derived from cache attacks and cache models using templates. These templates identify suspicious behavior that may lead to cache attacks. LiD-CAT is evaluated using two different cache architectures, one with a secure cache and one without. On each of them, SPEC2000 benchmarks are run together with malicious applications that execute cache attacks (i.e., Evict+Time, Prime+Probe, Flush+Reload and Flush+Flush). Results show that our lightweight detector successfully detects 99.99% of the attacks with less than 1% false-positives, has no timing penalties, and increases the area of a SoC with only 1.6%.

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Section: A Required Inputs For Cache Template Developmentmentioning

confidence: 99%

Section: B Integrationmentioning

confidence: 99%

Section: A Setupmentioning

confidence: 99%

Section: B Detectors Accuracymentioning

confidence: 99%

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