Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

Guo, Rui; Lu, Zhenghao; Hu, Shaogang; Yu, Qin; Rong, Liang; Liu, Yang

doi:10.3390/electronics10091009

Cited by 3 publications

(4 citation statements)

References 17 publications

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“…The reason for this is that T 1 and T 2 should be theoretically reached within 1 μs ( T r = 1 μs), but according to cases announced in 2021, their delay time was within 225 ns to 73 μs. Thus, the smaller the delay time, the better the module’s performance, allowing it to become superior [ 26 , 27 , 28 , 29 , 30 , 31 ]. In particular, the error for the delay time of the module was 1.8% compared to the delay time in [ 26 ], which could reach the 98.2% level for the accuracy, reliability, and reproducibility of the module [ 32 , 33 ].…”

Section: Discussionmentioning

confidence: 99%

The Design of an Automatic Temperature Compensation System through Smart Heat Comparison/Judgment and Control for Stable Thermal Treatment in Hyperthermic Intraperitoneal Chemotherapy (HIPEC) Surgery

Yoon

Lee

et al. 2023

Sensors

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After surgery for ovarian cancer or colorectal cancer, residual tumors are left around. A practical way to treat residual tumors is to destroy them with heat by injecting high-temperature drugs into the abdominal cavity. The injected medicinal substances are induced to flow out of the abdominal cavity; then, the spilled drug flows back into the abdominal cavity through feedback. During this process, the heat starts to decrease; thus, the treatment performance reduces. To overcome this problem, this study compares and assesses the temperature needed to maintain the heat for treatment and transmits a command signal to the heat exchanger through a look-up table (LUT). When the temperature decreases during the circulation of medications leaking out of the abdominal cavity, the LUT transmits a control signal (Tp) to the heat exchanger, which increases or vice versa. However, if the temperature (To) is within the treatment range, the LUT sends a Ts signal to the heat exchanger. This principle generates a pulse signal for the temperature difference (Tdif) in TC by comparing and determining the temperature (To) of the substance flowing out of the abdominal cavity with the reference temperature (Tref) through the temperature comparator (TC). At this time, if the signal is 41 °C or less, the LUT generates (heats) a Tp signal so that the temperature of the heat exchanger can be maintained in the range of 41 °C to 43 °C. If the Tdif is 44 °C or higher, the LUT generates (cools) the Ta signal and maintains the temperature of the heat exchanger at 41–43 °C. If the Tdif is maintained at 41–43 °C, the LUT generates a Tx signal to stop the system performance. At this time, the TC operation performance and Tdif generation process for comparing and determining the signal of To and Tref for drugs leaking out of the abdominal cavity is very important. It was observed that the faster the response signal, the lower the comparison and judgment error was; therefore, the response signal was confirmed to be 0.209 μs. The proposed method can guarantee rapid/accurate/safe treatment and automatically induce temperature adjustment; thus, it could be applied to the field of surgery.

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Section: Discussionmentioning

confidence: 99%

The Design of an Automatic Temperature Compensation System through Smart Heat Comparison/Judgment and Control for Stable Thermal Treatment in Hyperthermic Intraperitoneal Chemotherapy (HIPEC) Surgery

Yoon

Lee

et al. 2023

Sensors

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“…An adjustable reset delay module is added to the PFD to eliminate the dead-zone effects with different sets of process-voltage-temperature (PVT) conditions. The CP uses two rail-to-rail operational amplifiers to reduce the drain-voltage fluctuations in the metal-oxide-semiconductor field-effect transistor (MOSFET) in the current supply, with the goal of mitigating the mismatch between the charge and discharge currents introduced by channel-length modulation [16]. Moreover, a ring VCO architecture is adopted to reduce the chip area and cost, while providing a broadband tuning range [17].…”

Section: Pll Circuit Implementationmentioning

confidence: 99%

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

et al. 2022

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An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68.

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“…In addition, flip-flop (DFF of our design) rearranges the received data based on the reference clock, which in turn removes jitter accumulated in the input data across the various combination logic gates. In particular, according to a study by [24], the noise components by logic gates and DFF are less than −140 dBc, which is sufficiently small compared to the typical RSPD noise in Equation (3). Therefore, jitter accumulation from the conventional divider can be eliminated, and it can be thought that the noise element caused by the divider occurs only in a single DFF.…”

Section: Noise Analysismentioning

confidence: 99%

“…Recently, communication-based industries such as home IoT, 5G communications, autonomous vehicles, and mobile high-speed interfaces are growing rapidly [1][2][3][4]. Phase locked loop (PLL)-based clock generators are of particular interest in such applications, where the key characteristics are fine frequency resolution, excellent noise performance, low power consumption, and small chip area.…”

Section: Introductionmentioning

confidence: 99%

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator

Han

Eom

Choi

et al. 2021

Sensors

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Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.

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Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

Cited by 3 publications

References 17 publications

The Design of an Automatic Temperature Compensation System through Smart Heat Comparison/Judgment and Control for Stable Thermal Treatment in Hyperthermic Intraperitoneal Chemotherapy (HIPEC) Surgery

The Design of an Automatic Temperature Compensation System through Smart Heat Comparison/Judgment and Control for Stable Thermal Treatment in Hyperthermic Intraperitoneal Chemotherapy (HIPEC) Surgery

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator

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