Design and test of a 2-Gbit/s GaAs 16/8-bit MUX/DEMUX pair

Cheney, B.; Hamilton, Patricia; LaRue, G.

doi:10.1109/4.18609

IEEE J. Solid-State Circuits

1989

DOI: 10.1109/4.18609

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Design and test of a 2-Gbit/s GaAs 16/8-bit MUX/DEMUX pair

B. Cheney¹,

Patricia Hamilton²,

G. LaRue³

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Design and test of a 2-Gbit/s GaAs 16/8-bit MUX/DEMUX pair

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