Design and synthesis of synchronization skeletons using branching time temporal logic

Clarke, Edmund M.; Emerson, E. Allen

doi:10.1007/bfb0025774

Cited by 1,514 publications

(728 citation statements)

References 12 publications

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“…Note that we do not include in our CTL f logic the usual neXt temporal operator [3]. In fact, since we want to use CTL f to model analog properties, the notion of next point in time is meaningless in our context.…”

Section: Ctlf : a Temporal Logic For Spec-ification Of Analog Propertiesmentioning

confidence: 99%

Three-valued automated reasoning on analog properties

Gentilini

Schneider

Deisting

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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We deal with the problem of designing suitable languages for the modeling and the automatic verification of properties over analog circuits. To this purpose, we suitably enrich classical temporal logics with basic formulae allowing to model arbitrary functions relating analog variables. We show how to automatically check the resulting CTL f formulae on analog circuits. In particular, we rely on interval arithmetic methods and we extend to the analog context a number of techniques for the abstraction and the verification of digital systems, based on three-valued temporal logics. Categories and Subject Descriptors MOTIVATIONAnalog circuit design is of great importance in nowadays microelectronics [4,6]. In order to avoid a large number of defective prototypes, it is necessary to check significant properties of an analog circuit before manufacturing it. Traditionally, the above task relies largely on the cooperation of expert knowledge, manual calculation, and numerical circuit simulation [4]. A quite recent and active research field, named as symbolic analysis of analog circuits, aims at (1) endowing the verification process of some degree of automation (2) coping with variability of parameters and input signals [10,6,11]. The above objectives are fullfilled by providing computer algebra algorithms to simplify the mathematical model of an analog circuit. Typically, such procedures Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. work by detecting and deleting subformulae whose influence on the evolution of the system is insignificant. Despite the promising developments, system analysis is still far from being a completely automatic method for the verification of analog circuits.On the contrary, in the context of digital circuits, model checking allows to verify (1) entirely automatically (2) along all possible executions of the systems, properties that are formally stated in a temporal logic. A natural way to apply model checking to the context of analog circuits verification is the extraction of some finite digital abstraction from the corresponding analog model. Such an approach has been adopted in [5], where the authors qualitatively proved its effectiveness by applying it to some concrete (and well-understood) examples. As part of their work, the authors proposed an enrichment of classical temporal logic languages, recognizing the inadequacy of the latter to model analog properties. However, their extension is still not satisfactory: As an example, simple properties comparing the values of analog variables along their evolution can still not be dealt with in [5]. Indeed, even if a constraint of the kind x < y could be expressed in [5], a major pr...

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Section: Ctlf : a Temporal Logic For Spec-ification Of Analog Propertiesmentioning

confidence: 99%

Three-valued automated reasoning on analog properties

Gentilini

Schneider

Deisting

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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“…Emulating one step requires k moves, so that M answers in at most k ′ = k × max i (k i ) steps. Computation Tree Logic CTL [12] is also a well-known temporal logic for model checking. Since we mainly state a hardness result, there is no real need to recall its definition here.…”

Section: Linear Timementioning

confidence: 99%

A Parametric Analysis of the State Explosion Problem in Model Checking

2002

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In model checking, the state-explosion problem occurs when one checks a non-flat system, i.e., a system implicitly described as a synchronized product of elementary subsystems. In this paper, we investigate the complexity of a wide variety of modelchecking problems for non-flat systems under the light of parameterized complexity, taking the number of synchronized components as a parameter. We provide precise complexity measures (in the parameterized sense) for most of the problems we investigate, and evidence that the results are robust.

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“…Many properties of a transition system can be expressed in the Computation Tree Logic (CTL) [12]. Its formulas are built from propositions (predicates over the state variables), the usual Boolean operators, path quantifiers A (for all paths) and E (for some path), and modalities X (next-time), G (always), and W (weak until), among others, with every modality immediately preceded by a path quantifier.…”

Section: Symbolic Model Checkingmentioning

confidence: 99%

“…Note that this is essentially a backward breadth-first search. All other CTL formulas can be computed similarly as (possibly multiple) fixed points [12]. In so-called ªexplicitº model checking, a state set is represented simply by labeling individual states in the transition system.…”

Section: Symbolic Model Checkingmentioning

confidence: 99%

Optimizing symbolic model checking for statecharts

Chan

Anderson

Beame

et al. 2001

IIEEE Trans. Software Eng.

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AbstractÐSymbolic model checking based on binary decision diagrams is a powerful formal verification technique for reactive systems. In this paper, we present various optimizations for improving the time and space efficiency of symbolic model checking for systems specified as statecharts. We used these techniques in our analyses of the models of a collision avoidance system and a faulttolerant electrical power distribution (EPD) system, both used on commercial aircraft. The techniques together reduce the time and space requirements by orders of magnitude, making feasible some analysis that was previously intractable. We also elaborate on the results of verifying the EPD model. The analysis disclosed subtle modeling and logical flaws not found by simulation.

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Design and synthesis of synchronization skeletons using branching time temporal logic

Cited by 1,514 publications

References 12 publications

Three-valued automated reasoning on analog properties

Three-valued automated reasoning on analog properties

A Parametric Analysis of the State Explosion Problem in Model Checking

Optimizing symbolic model checking for statecharts

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