Design and Synthesis of a High-Speed Hardware Linked-List for Digital Image Processing

Abstract

To deal with the problem of maintaining variable data set in digital image processing, this paper brings forward a general hardware structure for linked-list. It is designed to accomplish the commonly used functions and some more complicated functions of the linked-list data structure. In order to fully utilize the limited memory resources in embedded hardware platform, we propose a memory recycle scheme to reuse the memory space where the data have been deleted. In our work, the length of the linked-list is parameterized and can be reconfigured. The structure is mapped onto an FPGA chip. Experimental results show that our proposal works functionally well. Only few hardware resources are used and it consumes pretty low power. According to the length of the list, clock speed from 100MHz up to 200MHz is achieved. Compared with the software linkedlist structure in PC, our proposal in FPGA achieves 170.4 times of speedup in average. Our design has been utilized into people tracking system successfully.

Improving high-level synthesis with decoupled data structure optimization

“…Several recent studies have investigated the benefits of specialized data structure accelerators to eliminate memory accesses and improve the performance of data and instruction caches [16]. Hardware implementations of some data structures have been reported including linked lists [18], queues [1,7], trees [11,2], and other pointer-based structures [12,15]. Our work focuses on synthesizing container units for a broader range of complex data structures, instead of crafting the most efficient implementation of a specific structure.…”