Design and Simulation of Steep-Slope Silicon Cold Source FETs With Effective Carrier Distribution Model

Steep Slope Field Effect Transistors Based on 2D Materials

“…[136] 3D Dirac materials include superlattices and p type-metaln type or reversely configurated broken band diagrams structures. [137][138][139] Superlattice source FETs mainly entrusted superlattice structures in source extensions to filter out higher energy electrons entering into devices channels to achieve a steep subthreshold slope. Higher I on and sub-thermionic SS are capable of being attained by engineering the superlattice structures interposed in source extensions through an accurate selection of the constituent materials or by adjusting the superlattice physical dimensions, which are widely constructed by III-V semiconductor materials.…”

“…[137] Using InGaAs-InAlAs pairs as components of superlattice structure interposed in source extensions, E. Gnani obtained a SS of 13 mV dec −1 and an on-state current I ON of 4.5 mA μm −1 under V DD of 0.4 V, which outperformed the ITRS requirements for 21 nm technology node. [138] Weizhuo Gan and coworkers realized a Si cold source FET (CSFET) by a broken-gap-like p-Si/metal/n-Si cold source (CS), which cut off thermal tail of carriers by bandgap and suppressed the hot carriers injection, leading to a steeper SS, [139] correspondingly, a reverse typed Si CSFET could be realized by n-Si/metal/p-Si broken band structures, which was also sufficiently studied to obtain a sub-thermionic SS. [140] 3D Dirac source materials mainly aim at achieving steep switching behavior in Si based FET by engineering source DOS to cut off thermal tail of high energy carriers to suppress hot carriers injection, which is relatively compatible with modern Si fabrication process in compared with DSFETs based on 2D materials.…”

“…[136] Noble 2D TMD materials as of PbS 2 is verified to be to be fabricated 2D lateral heterojunction 2D DSFET with bulk PbS 2 as cold injection source and monolayer PbS 2 as channel, opening new gateways for fabricating lateral heterojunctions free of interfaces states for applications in low power dissipation electronics. [135] Dirac sources are also compatible with various kinds of device structures, including double gated Si FET, [139] Si GAAFET structure, [137,138] 2D FET [21,33,133] or 2D GAAFET structure, [141] which provides further opportunities to combine cold Dirac sources injection with other kinds of steep slope structures including NCFET, to make full use of the merits of all kinds of steep slope components to attain high performance with low power dissipation.…”

Ambipolar steep-slope nanotransistors with Janus MoSSe/graphene heterostructures

“…Fortunately, a sharp Schottky-barrier with effective gate tuning can form at van der Waals (vdW) source/channel contacts due to the weak Fermi level pinning effect [15]. Therefore, CS FETs based on 2D vdW heterostructures have been proposed and studied experimentally and theoretically [13,14,[16][17][18][19][20][21][22].…”

Strain engineered C31 field-effect-transistors: a new strategy to break 60 mV/decade by using electron injection from intrinsic isolated states

“…One is the vertical heterostructure, which is van der Waals coupling; [13][14][15][16][17] the other one is the lateral heterostructure with a cold source of semiconductor/metal/semiconductor structure. 18) However, the complicated heterostructure can be hardly implemented in the CMOS compatible process. Thus, how to design a device with a simple structure with steep slope is extremely necessary.…”