Design and simulation of high speed comparator for LVDS receiver application

Sujatha, K.; Bhagirath, T. Narayana; Garje, Kiran Kumar

doi:10.1109/indicon.2015.7443604

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Cited by 9 publications

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“…The proposed comparator scheme is represented in Figure 3. It is composed of three stages of a different nature, as indicated above, to be more insensitive to noise and process variations [15], [16]. 1 is used to constructing the logic circuit in Figure 6.…”

Section: Sub-adc Blockmentioning

confidence: 99%

The 1.5 bit-per-stage 10-bit pipelined CMOS A/D converter for CMOS image sensor

Menssouri,

El Khadiri,

Tahiri

2023

IJPEDS

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<span lang="EN-US">This paper presents a 1.5-bit/stage pipeline analog-to-digital converters (ADC) with a 100 MHz operating frequency for CMOS image sensors built using TSMC 90nm CMOS technology. The design features a novel architecture including a comparator, CMOS transmission gates, a sub-ADC logic circuit, bootstrap switches, and a gain-boosted fully differential telescopic op-amp based switched-capacitor MDAC. The ADC operates on a 1.8 V power supply, with a typical power dissipation of 1.632 mW, and a full-scale input signal voltage of 0.8 V. At 100 MHz sampling frequency, it achieves a maximum ENOB of 12.42 bits, an SNR of 76.53 dB, and a FOM of 0.297 pJ/conversion step. This 1.5-bit/stage pipeline ADC is well-suited for CMOS image sensors.</span>

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Section: Sub-adc Blockmentioning

confidence: 99%