Design and performance of low-current GaAs MMICs for L-band front-end applications

Imai, Yasuhiko; Tokumitsu, M.; Minakawa, Akira

doi:10.1109/22.102962

Cited by 58 publications

(4 citation statements)

References 12 publications

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“…1(a), the desired input impedance of the amplifier is obtained for a narrow frequency band by choosing and independently. When , it is approximated as follows [5]: (18) It is known that the source degeneration inductance controls the noise performance of the given architecture [14], but the reasons are not well understood.…”

Section: Design Considerations For a Tuned Amplifiermentioning

confidence: 99%

A noise optimization technique for integrated low-noise amplifiers

Goo

Ahn

Ladwig

et al. 2002

IEEE J. Solid-State Circuits

115

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Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near min by choosing an appropriate device geometry along with an optimal bias condition. An 800-MHz LNA has been implemented in a standard 0.24m CMOS technology. The amplifier possesses a 0.9-dB noise figure with a 7.1-dBm third-order input intercept point, while drawing 7.5 mW from a 2.0-V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

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Section: Design Considerations For a Tuned Amplifiermentioning

confidence: 99%

A noise optimization technique for integrated low-noise amplifiers

Goo

Ahn

Ladwig

et al. 2002

IEEE J. Solid-State Circuits

115

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“…A dual gate MESFET with a gate width of 200 pm is used for the LNA. The input matching circuit is constructed by the series and shunt spiral inductors [5].…”

Section: Mmic Designmentioning

confidence: 99%

A high performance GaAs MMIC transceiver for personal handy phone system (PHS)

Fujimoto

Kunihisa

Yamamoto

et al. 1995

1995 25th European Microwave Conference

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A high perormance GaAs MMIC transceiver has been developed for the Personal Handy phone System (PHS), Japan's digital cordless telephone system. The MMIC includes a T/R switch, a Low Noise Amplifier (LNA) and a Power Amplifier (PA), which offers significant advantages in RF performance in comparison with silicon devices. In receive mode, the power gain and the noise figure including T/R switch are 15 dB and 2.4 dB, respectively. In transmit mode, the MMIC including T/R switch exhibits an overal power added efficiency (PAE)-of 25.5% and produces an output power of 21 dBm with an adjacent channel leakage power (Padj) of -56.2 dBc (600 kHz offset) at 1.9 GHz for i/4-shift OPSK modulated signal. A very small chip size of 1.0 mm x 2.7 mnm is also realized. This is one of the smallest GaAs MMICs that have been reported with the same functionality.

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“…This makes broadband matching very difficult. Earlier approaches used wide transistors [4], [5] or high Q inductors [2] to overcome this problem. At a fixed dc power consumption, this costs gain, chip size and the transistors can not be biased for optimum noise figure [4], [ 5 ] .…”

Section: Introductionmentioning

confidence: 99%

Novel design topology for ultra low power down converters with broadband on chip matching network

Schmatz

Lott

Baumberger

et al. 1995

IEEE Trans. Microwave Theory Techn.

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A novel design topology for ultra low power receivers and down converters has been developed. Using this topology, a monolithic L-band down converter consisting of an input amplifier and a double balanced mixer has been impiemented with a standard 0.7 pm GaAs-MESFET process. The circuit has a single ended 50 R input and differential outputs offering totally more than 40 dB voltage conversion gain at 1 GHz and 30 clB at 2 GHz. It is supplied by a single lithium cell and has a dc power consumption of less than 2.0 mW at 2.7 V. Through a more exact modeling of the parasitic capacitance of n-implanted resistors an improved agreement between measurement and simulation was achieved. Finally, the determination of the noise figure at a high impedance output from a 50 R measurement is presented.In 1987, he joined the Laboratory for Electromagnetic Fields and Microwave Electronics of ETH, where he copioneered the research activities on the design of low power analog and mixed LSI GaAs integrated circuits. His research work has concentrated on the design of IC's for optical and wireless communication in both GaAs MESFET and high speed silicon bipolar technology, and process variation modeling of MESFET devices.

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Design and performance of low-current GaAs MMICs for L-band front-end applications

Cited by 58 publications

References 12 publications

A noise optimization technique for integrated low-noise amplifiers

A noise optimization technique for integrated low-noise amplifiers

A high performance GaAs MMIC transceiver for personal handy phone system (PHS)

Novel design topology for ultra low power down converters with broadband on chip matching network

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