Design and performance evaluation of a low cost Full Protected CMOS Latch

Shirinzadeh, Saeideh; Asli, Rahebeh Niaraki

doi:10.1109/cads.2013.6714254

Cited by 5 publications

(15 citation statements)

References 9 publications

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“…After 3 years of operation, it exceeds 90% of the value after 6 years for all nodes and input probabilities. Moreover, considering the standard latch and the robust latches in category 1, we can see that node B in the standard latch, node In1 in the latch in [7], and node Q in the latches in [8,10] exhibit the lowest value of Qcrit for all considered operating time. This holds true for all considered input probabilities.…”

Section: B Impact Of Bti On the Critical Chargementioning

confidence: 90%

“…Robust latches can be divided in two categories, depending on how their increased robustness against SETs is achieved [6]. One category, hereinafter referred to as category 1, consists of latches made robust by increasing the capacitance of some of their nodes and/or the driving strength of some transistors (e.g., the latches proposed in [7,8,9,10]). These approaches usually require low area overhead, but do not guarantee complete immunity against SEs.…”

Section: Index Terms-static Latch; Robust Latch; Soft Error; Aging;mentioning

confidence: 99%

“…They are: 1) the latch in [32] (Fig. 1(a)), as an example of standard latch; 2) the robust latches recently proposed in [7], [8] and [10] (Figs. 1(b), 1(c) and (d), respectively) that belong to category 1; 3) the robust latches recently proposed in [6] and [14] (Figs.…”

Section: A Simulation Setupmentioning

confidence: 99%

“…1(a)); in1, nQ, Io1 and D, for the robust latch in [7] (Fig. 1(b)); Q and D, for the robust latches in [8] and [10] (Figs. 1(c) and 1(d)).…”

Section: A Simulation Setupmentioning

confidence: 99%

“…Moreover, the nodes with the highest reduction in the Qcrit value after t=6 years are: node B in the standard latch (Qcrit = -17.4%), node D in the robust latch of category 1 in [7] (Qcrit = -20.2%), and node D in the robust latches of category 1 in [8] and [10] (Qcrit = -20.3% and 14.8%, respectively). As for the robust latches of category 2 in [14,6], their input node, which is their only susceptible node, presents a 16.8% and 20.2% Qcrit reduction, respectively.…”

Section: B Impact Of Bti On the Critical Chargementioning

confidence: 99%

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Impact of Aging Phenomena on Latches’ Robustness

Omaña

Rossi

Edara

et al. 2016

IEEE Trans. Nanotechnology

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk TNANO-00456-2015 1  Abstract-In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider Bias Temperature Instability (BTI) affecting both nMOS (positive BTI) and pMOS (negative BTI), which is considered the most critical aging mechanism threatening the reliability of ICs. Our analyses show that, as an IC ages, BTI increases significantly the susceptibility of both standard latches and low-cost robust latches, whose robustness is based on the increase in the critical charge of their most susceptible node(s). Instead, we will show that BTI minimally affects the soft error susceptibility of more costly robust latches that avoid the generation of soft errors by design. Consequently, our analysis highlights the fact that, in applications mandating the use of low-cost robust latches, designers will have to face the problem of their robustness degradation during IC lifetime. Therefore, for these applications, designers will have to develop proper low-cost solutions to guarantee the minimal required level of robustness during the whole IC lifetime.

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Section: B Impact Of Bti On the Critical Chargementioning

confidence: 90%

Section: Index Terms-static Latch; Robust Latch; Soft Error; Aging;mentioning

confidence: 99%

Section: A Simulation Setupmentioning

confidence: 99%

“…1(a)); in1, nQ, Io1 and D, for the robust latch in [7] (Fig. 1(b)); Q and D, for the robust latches in [8] and [10] (Figs. 1(c) and 1(d)).…”

Section: A Simulation Setupmentioning

confidence: 99%

Section: B Impact Of Bti On the Critical Chargementioning

confidence: 99%

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Impact of Aging Phenomena on Latches’ Robustness

Omaña

Rossi

Edara

et al. 2016

IEEE Trans. Nanotechnology

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A High Performance SEU Tolerant Latch

2015

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This paper presents and analyzes a high performance latch tolerating single event upsets (SEU) in 45 nm CMOS technology. The internal nodes of the latch are immune to SEUs by combining Muller C-elements with dual modular redundancy and interlocked feedback. The output nodes are SEU resilient and allow a recovery to the correct logic value when an SEU occurs at output nodes. The power dissipation, propagation delay and critical charge of the proposed SEU-tolerant latch are evaluated and discussed with SPICE simulations. The simulation results show that the proposed latch achieves a better tradeoff among soft error rate, delay, power and area than previous hardened latches. On average the HPST latch requires 70.31 % area overhead, but improves the critical charge by 71.05 % and reduces the power delay product by 51.96 %. It is thus an excellent solution for applications requiring both high performance and high reliability. Monte Carlo simulation also verifies the robustness of the proposed latch in presence of process, temperature and voltage (PVT) variations.

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Unique robust fault resistant D-latch for low power applications

Singar

Ghosh

2017

2017 International Conference on Computer, Communications and Electronics (Comptelix)

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Design and performance evaluation of a low cost Full Protected CMOS Latch

Cited by 5 publications

References 9 publications

Impact of Aging Phenomena on Latches’ Robustness

Impact of Aging Phenomena on Latches’ Robustness

A High Performance SEU Tolerant Latch

Unique robust fault resistant D-latch for low power applications

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