A High Performance SEU Tolerant Latch

Abstract

This paper presents and analyzes a high performance latch tolerating single event upsets (SEU) in 45 nm CMOS technology. The internal nodes of the latch are immune to SEUs by combining Muller C-elements with dual modular redundancy and interlocked feedback. The output nodes are SEU resilient and allow a recovery to the correct logic value when an SEU occurs at output nodes. The power dissipation, propagation delay and critical charge of the proposed SEU-tolerant latch are evaluated and discussed with SPICE simulations. The simulation results show that the proposed latch achieves a better tradeoff among soft error rate, delay, power and area than previous hardened latches. On average the HPST latch requires 70.31 % area overhead, but improves the critical charge by 71.05 % and reduces the power delay product by 51.96 %. It is thus an excellent solution for applications requiring both high performance and high reliability. Monte Carlo simulation also verifies the robustness of the proposed latch in presence of process, temperature and voltage (PVT) variations.

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

“…19(a), the power dissipation increases along with the value of supply voltage. The power dissipation quadratically depends on the supply voltage, and hence the power dissipation of all the hardened latches increases when the supply voltage increases [26]. Further, compared with the same type latches, the power dissipation of the proposed latch has less sensitivity to supply voltage, and the sensitivity orders are: LSEH2 ≥ FERST N LCHR N LSEH1 ≥ Proposed.…”

“…As we can see, both the power dissipation and the delay increase along with the value of temperature. The main reason is the decreasing of the device carrier mobility [26]. Further, compared with the same type latches, the power dissipation and D-Q delay of the proposed latch has equivalent or just a little more sensitivity to the temperature variation, and the sensitivity orders are: FERST N LSEH1 ≥ LSEH2 N LCHR ≥ Proposed, and FERST ≥ LSEH2 N LCHR ≥ Proposed N LSEH1, respectively.…”

A transient pulse dually filterable and online self-recoverable latch

“…The simulation conditions are listed below. 1) 32 nm technology, PTM model [11]; 2) 0.9 V supply voltage and room temperature; 3) 0.5 GHz working clock frequency; 4) Double exponential current source model for SET and SEU injections [6,7,8]. Fig.…”

“…Recently, many schemes about latch hardening against SET or SEU have been proposed [3,4,5,6,7,8,9, 10] and these schemes could be divided into three categories: 1) SEU not immune ones [3,4], i.e. there is at least one weak node and if the node is flipped by an SEU the latch would retain invalid data; 2) SEU immune but SET not filterable ones [5,6,7,8], i.e. the output would not retain invalid data no matter which node of the latch is affected by an SEU, but cannot filter an SET; 3) SEU immune and SET filterable ones [9,10].…”

Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

“…This saves power dissipation. The majority voter circuit designed with less number of transistors and less sensitive nodes compared to the existing classical TMR latch used in [12]. With less number of sensitive nodes, the probability of affecting the circuit due to transient faults is also less.…”