Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

Abstract

in this paper, we discuss a method to extrapolate intrinsic and extrinsic Ron components for a JFET. The results provide the guideline to lower Ron, hence to achieve competitive "Ron vs. pinch off (Voff)" benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The optimized JFET demonstrates the 50% lowered Ron, low Voff of -2.75V, and high BVdss of 11V.