Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

Jacquemod, G.; Geynet, L.; Nicolle, B.; Foucauld, Emeric de; Tatinian, William; Vincent, Pierre

doi:10.1016/j.mejo.2008.01.069

Cited by 11 publications

(4 citation statements)

References 4 publications

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“…Since the VCO is used in a PLL, the previous measured phase noise spectrum depicted has been adopted in a PLL linear Matlab model [24]. The cut-off frequency of the loop filter has been designed having in mind the minimization of the PLL integrated phase noise.…”

Section: Pll Implementationmentioning

confidence: 99%

A 12 GHz 30 mW 130 nm CMOS Rotary Travelling Wave Voltage Controlled Oscillator

Jacquemod

Abdeljelil

Carpineto³

et al. 2012

Active and Passive Electronic Components

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This paper reports a 12 GHz rotary travelling wave (RTW) voltage controlled oscillator designed in a 130 nm CMOS technology. The phase noise and power consumption performances were compared with the literature and with telecommunication standards for broadcast satellite applications. The RTW VCO exhibits a −106 dBc/Hz at 1 MHz and a 30 mW power consumption with a sensibility of 400 MHz/V. Finally, requirements are given for a PLL implementation of the RTW VCO and simulated results are presented.

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Section: Pll Implementationmentioning

confidence: 99%

A 12 GHz 30 mW 130 nm CMOS Rotary Travelling Wave Voltage Controlled Oscillator

Jacquemod

Abdeljelil

Carpineto³

et al. 2012

Active and Passive Electronic Components

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“…At the beginning, the frequency difference of the PLL is very large, so the circuit turns to steady state mainly depending on the error voltage of frequency detector. Otherwise, after the circuit enters into the rapid capture band, the frequency difference is small and the voltage of phase difference (the output of PD) will mainly lead the PLL circuit into locked state (steady state) [10].…”

Section: A Pll System Designmentioning

confidence: 99%

Design and Implementation of Ultrasonic Velocity Measuring Module Based on Phase-Locked Loop

Ding¹,

Peng²,

Han³

2012

JCP

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Due to the important relationship between ultrasonic velocity and some properties of sample, the measurement of velocity of ultrasound is widely needed in various fields. In this paper, based on phase-locked loop technique, a new hybrid circuit is designed for ultrasonic velocity measurement and named as UV-PLL. In order to improve the stability of phase and achieve the ability of fast locking, an auxiliary capturing circuit, which consists of phase shift circuit and capturing circuit, is designed and implemented in this module. Additionally, two methods for estimating the propagation delay is compared and described in detail. The UV-PLL module is validated through the ultrasonic velocity measurement in distilled water at different temperatures. Experimental results show that the maximum relative deviation of velocity measurement is less than 0.15% and the loop can be quickly locked, indicating that this module can meet the requirements of online measurement and can be widely applied.

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“…The cut-off frequency of the loop filter has been designed having in mind the minimization of the PLL integrated phase noise. Figure 12 plots the integrated phase noise error versus the open loop bandwidth as computed by the linear model [14]. The minimum phase error is 1.6° RMS with a 550 kHz optimal bandwidth for the RTW VCO PLL (cf.…”

Section: Rtw and Lc Qvco Designmentioning

confidence: 99%