Design and modeling of low-power clockless serial link for data communication systems

Alser, Mohammed; Assaad, Maher

doi:10.1109/natpc.2011.6136441

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…We design our hardware accelerator to exploit the large amounts of parallelism offered by FPGA architectures [114,123,124,127,128,129,130,131,132]. We take advantage of the fact that alignment filtering of one read is inherently independent of filtering of another read.…”

Section: Parallelizationmentioning

confidence: 99%

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

Alser

2019

Preprint

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Section: Parallelizationmentioning

confidence: 99%

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

Alser

2019

Preprint

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“…These advances allow the number of integrated modules to grow much more rapidly on a single chip [1] or in a single package. These technologies will require a large number of parallel wiring nets and buses for interconnections as well as data communication between these modules.…”

Section: Introductionmentioning

confidence: 99%

Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers

Jaiswal¹,

Gamad²

2015

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The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.

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“…On-chip serial links have been previously proposed as a strong solution to reduce the complexity and/or the energy dissipation of on-chip interconnect fabrics [1]. Meanwhile, the serial link fulfills the strongly emerging need for a higher-speed, more efficient data transmission, and longer distance reach [2]. Currently, serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.…”

Section: Introductionmentioning

confidence: 99%

“…Currently, serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical. Its applications span every sector of the communication and networking applications, which use high speed intra/inter chip communication [2]. The serial link system typically consists of three main components, including the serializer (i.e.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

Assaad¹,

Alser²

2011

IEICE Electron. Express

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Abstract:In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two signals without jitter accumulation issue. Moreover, it can be easily adapted for different FPGA families as well as implemented as an integrated circuit. The proposed serializer circuit is used as a part of a SERDES in inter-module communication in system-on-chip (SoC). The simulation and experimental results confirm the performance of the serializer with the proposed clock multiplier. Keywords: field programmable gate array (FPGA), system-on-chip (SoC), all-digital serializer, clock multiplier. Classification: Electron devices, circuits, and systems References

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Design and modeling of low-power clockless serial link for data communication systems

Cited by 5 publications

References 10 publications

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers

An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

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