An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

Assaad, Maher; Alser, Mohammed

doi:10.1587/elex.8.2017

Cited by 5 publications

(3 citation statements)

References 6 publications

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“…We design our hardware accelerator to exploit the large amounts of parallelism offered by FPGA architectures [114,123,124,127,128,129,130,131,132]. We take advantage of the fact that alignment filtering of one read is inherently independent of filtering of another read.…”

Section: Parallelizationmentioning

confidence: 99%

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

Alser

2019

Preprint

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Section: Parallelizationmentioning

confidence: 99%

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

Alser

2019

Preprint

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“…The input to the 16-phase generator is from the DCO (digitally controlled oscillator) which is already implemented in [4]. The output of the DCO is given as clock signal to the 16-phase generator.…”

Section: A 16-phase Generatormentioning

confidence: 99%

A novel FPGA based digital octa-rate clock and data recovery circuit

Sankalp

Reddy

Kumar

et al. 2015

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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Clock and data recovery (CDR) circuit in general, plays a vital role for serial-link communication in multi-module based System on chip (SOC). It uses a high frequency clock to handle high data rate, which results in high dynamic power consumption. In order to reduce the high dynamic power consumption, the proposed design works at the one-eighth frequency of the received data rate and presents a novel digital octa-rate clock and data recovery circuit as an optimal solution. The octa-rate CDR circuit consists of 16-phases generator, delay line controller, an octa-rate early-late type phase detector and digitally controlled delay line. The purpose of delay line controller is to provide sufficient delay in digitally controlled delay line. It is observed from literature that the existing delay line controller is realized by using combinational circuit which is not providing sufficient delay. Hence, in this work we introduced Finite State Machine (FSM) based delay line controller to provide sufficient delay. In order to reduce dynamic power consumption, a novel octa-rate CDR circuit has been realized using Xilinx ISE 13.2 and implemented on Vertex-5 FPGA target device for real time verification. Corresponding results shows a significant dynamic power reduction. Keywords-clock and data recovery circuit (CDR); systemon-chip(SOC); octa-rate early-late type phase detector;FSMI.

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“…Moreover, the proposed architecture is portable and can be easily implemented as an integrated circuit. The simultaneous dual properties enhance the stability of the system and can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC) [11].…”

Section: Operation Overviewmentioning

confidence: 99%

Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture

Assaad

Alser

2012

VLSI Design

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This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit. Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC). The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. The experimental results validate the expected phase tracking as well as the synthesizing properties. For the measurement and validation purpose, an input reference signal in the range of 1.94–2.62 MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2–167.9 MHz with a frequency step (i.e., resolution) of 0.168 MHz. The synthesized design requires 330 logic elements using the above Altera board.

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An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

Cited by 5 publications

References 6 publications

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design

A novel FPGA based digital octa-rate clock and data recovery circuit

Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture

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