Design and integration of electrical-based dimensional process-window checking infrastructure

Abstract

The purpose of this work is to provide a design infrastructure for electrical-based dimensional processwindow checking. With the aid of the novel test vehicle design platform, the discrepancy among design rule set, test structure design and testing plan can be minimized. Using the function-independent Test Structure Design Intellectual Properties (TSD-IP) provided by this infrastructure, the process-window could be quantified as the electrical testing of test structures. A cross-generation (130nm-90nm) test vehicle which focus on the evaluation of overlay and critical dimension variation cross the intra-and inter-photo field is enacted to demonstrate the design framework.Index Terms-test structure, test vehicle, logic process, SoC, electronic design automation, synthesis, and migration. IntroductionAs sub-wavelength semiconductor process rapidly proliferates, the resolution requirement of metrology, three sigma deviation of actual image sizes on a wafer, is scaling down to the range of tens nanometer. As 100 nm metrology specification stated in the SIA 1999, wafer gate and dense line CD control node are 5.9 nm and 10 nm; wafer overlay and output metrology precision control are 35 nm and 3.5 nm [I]. As for the metrology of nanometer accuracy such as scanning electron microscopy of non-destructive measurement or transmission electron microscopy of destructive measurement, is typical either inline or off-line metrology tool. To scrutinize information regarding the distribution profile of wafer level, large amounts of data must be collected. In a practical application, the cost of measurement and wafer scrapping caused by destructive sample preparation is usually prohibitive. Moreover, to distinguish the similarity and difference variations among die-to-die (DZD), wafe-to-wafer (WZW), and lotto-lot (LZL), it will multiply the cost and measurement time. In the abovementioned, electrical-based parameter extraction with statistical methodology is the most appropriate solution [2]-[3]. To provide a'qualified parametric test chip or test vehicle, it relays on an appropriate infrastructure including mask set generation (mainly GDS or CIF formatted), testing and analysis. Among those, test structure design and system of mask set generation are foundations that are designed to investigate or diagnose electrical performance parametric test vehicle. Lukaszek er al. [4] reviewed a comprehensive test structure of CMOS yield problems. A standardized test structure design format was proposed for ASIC-oriented process development [SI. Precise measurement methodology and test structures of critical dimension and layer-to-layer registration were proposed in [6]-191. A parametric tcst computer-aid design was implemented by Ternisien et 01. [IO]. Kumar el al. [I I] proposed a test chip design environment, which is based on commercial layout tool and uses in-house software to link with parametric test system. L. Kasel el ai. [I21 presented a platform, which automatically generates test mask and measurement databases for SPICE model char...

Infrastructure Development and Integration of Electrical-Based Dimensional Process Window Checking

“…13, where the test structures created by this framework are located in the center and at the four corners of the photofield. Two major test structure sets are used in [26] and [28], called the dimensional sensitive set and the mechanical stress sensitive set. The former includes the van der Pauw, four-port Kelvin, continuity and bridging test structures, among others [26].…”

“…Two major test structure sets are used in [26] and [28], called the dimensional sensitive set and the mechanical stress sensitive set. The former includes the van der Pauw, four-port Kelvin, continuity and bridging test structures, among others [26]. The latter is designed to study the mechanisms involved in geometry-dependent stress-induced electrical performance changes, as discussed in [28], which includes the via-chains structures with various volume ratios of the upper metal runner to the via,and similar volume ratios of the lower metal laid-pad to the via.…”

“…9 from the unit-cell to the edge of the block is designed for the metal interconnection and active/poly layers, thus preventing stress that would otherwise be induced by a change in the geometry of the local layout [25], [26]. After the blocks are con- structed, a pin or text label is assigned to the connector prior to metal routing.…”