Design and integration considerations for end-of-the roadmap ultrashallow junctions

Osburn, C. M.; De, Indranil; Yee, K. F.; Srivastava, A.

doi:10.1116/1.591195

Cited by 24 publications

(12 citation statements)

References 16 publications

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“…The deeper the SDE, the higher the SCE, and spreading of the depletion region into the channel. However, the trade off between shallow SDE is an increase in the series resistance of the transistor [18].…”

Section: Halo Dopingmentioning

confidence: 99%

Impact of technology scaling on leakage reduction techniques

Ghafari

Anis

Elmasry

2007

2007 IEEE Northeast Workshop on Circuits and Systems

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CMOS technology is scaling down to meet the performance, production cost, and power requirements of the microelectronics industry. The increase in the transistor leakage current is one of the most important negative side effects of technology scaling. Leakage affects not only the standby and active power consumption, but also the circuit reliability, since it is strongly correlated to the process variations. Leakage current influences circuit performance differently depending on: operating conditions (e.g., standby, active, burn in test), circuit family (e.g., logic or memory), and environmental conditions (e.g., temperature, supply voltage). Until the introduction of high-K gate dielectrics in the lower nanometer technology nodes, gate leakage will remain the dominant leakage component after subthreshold leakage.[1] Since the way designers control subthreshold and gate leakage can change from one technology to another, it is crucial for them to be aware of the impact of the total leakage on the operation of circuits and the techniques that mitigate it.Consequently, techniques that reduce total leakage in circuits operating in the active mode at different temperature conditions are examined. Also, the implications of technology scaling on the choice of techniques to mitigate total leakage are investigated. This work resulted in guidelines for the design of low-leakage circuits in nanometer technologies. Logic gates in the 65nm, 45nm, and 32nm nodes are simulated and analyzed. The techniques that are adopted for comparison in this work affect both gate and subthreshold leakage, namely, stack forcing, pin reordering, reverse body biasing, and high threshold voltage transistors. Aside from leakage, our analysis also highlights the impact of these techniques on the circuit's performance and noise margins.The reverse body biasing scheme tends to be less effective as the technology scales since this scheme increases the band to band tunneling current. Employing high threshold voltage transistors seems to be one of the most effective techniques for reducing leakage with minor performance degradation. Pin reordering and natural stacks are techniques that do not affect the performance of the device, yet they reduce leakage. However, it is demonstrated that they are not as effective in all types of logic since the input values might switch only between the highly leaky states.Therefore, depending on the design requirements of the circuit, a combination, or hybrid iii of techniques which can result in better performance and leakage savings, is chosen. Power sensitive technology mapping tools can use the guidelines found as a result of the research in the low power design flow to meet the required maximum leakage current in a circuit. These guidelines are presented in general terms so that they can be adopted for any application and process technology. iv AcknowledgementsThis research project would not have been possible without the support of many people.

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Section: Halo Dopingmentioning

confidence: 99%

Impact of technology scaling on leakage reduction techniques

Ghafari

Anis

Elmasry

2007

2007 IEEE Northeast Workshop on Circuits and Systems

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“…1 The requirement becomes more and more rigorous as the device is scaled into sub-50 nm scale, and is simply not achievable with standard technology due to solid-solubility limitations and sheet resistance ͑R S ͒ rise as junction depth ͑X J ͒ drops. 1 The requirement becomes more and more rigorous as the device is scaled into sub-50 nm scale, and is simply not achievable with standard technology due to solid-solubility limitations and sheet resistance ͑R S ͒ rise as junction depth ͑X J ͒ drops.…”

Section: Introductionmentioning

confidence: 99%

Quantitative analysis of ultrashallow junction of sub-50nm gate-length transistors: Junction depth, sheet resistance, short channel effects, and transistor performance

Buh

Park

Yon

et al. 2006

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inDopant profiling in vertical ultrathin channels of double-gate metal-oxide-semiconductor field-effect transistors by using scanning nonlinear dielectric microscopy Appl. Phys. Lett. 85, 4139 (2004); 10.1063/1.1812571 Secondary ion mass spectrometry characterization of source/drain junctions for strained silicon channel metal-oxide-semiconductor field-effect transistors Two-dimensional ultrashallow junction characterization of metal-oxide-semiconductor field effect transistors with strained silicon Two-dimensional dopant concentration profiles from ultrashallow junction metal-oxide-semiconductor field-effect transistors using the etch/transmission electron microscopy method Shallow junctions diffused from single-and coimplanted WSi 2 films and integrated 0.2 μm complementary metal-oxide-semiconductor transistorsWe analyzed causes of dopant loss in ultrashallow junction during complementary metal-oxide-semiconductor ͑CMOS͒ fabrication: ͑1͒ sputtering-out during ion implantation, ͑2͒ wet-etching removal in cleaning process, ͑3͒ outdiffusion, and ͑4͒ deactivation in post-thermal process. By using low energy electron induced x-ray emission spectrometry and other conventional analytic techniques such as four-point probe ͑FPP͒ and SIMS, the dopant losses are quantified. We developed a simple source/drain extension ͑SDE͒ sheet-resistance test structure to measure the actual sheet resistance of SDE to avoid sizable error due to FPP probe penetration. By comparing with CMOS electrical data, practical aspect of junction depth and sheet resistance is discussed in terms of short channel effects and on-state current. It is found that deactivation and wet-etching removal of arsenic dopant during cleaning process are the major factors in scaling of n-type transistor, while junction depth is the major one in scaling of p-type transistor.

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“…1 For dopant profiling secondary ion mass spectrometry ͑SIMS͒ has become a generally accepted method with excellent sensitivity and nmdepth resolution. 1 For dopant profiling secondary ion mass spectrometry ͑SIMS͒ has become a generally accepted method with excellent sensitivity and nmdepth resolution.…”

Section: Introductionmentioning

confidence: 99%

Spreading resistance roadmap towards and beyond the 70 nm technology node

Vandervorst

Clarysse

Eyben

2002

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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The manufacturing of deep submicron devices requires the formation of very shallow, highly doped source/drain profiles. Besides the need to determine the correct atomic dopant distribution ͑using secondary ion mass spectrometry͒, there is an increasing demand for the accurate determination of the electrical carrier profiles related with the need to monitor the activation of the dopants under reduced thermal budgets. Conventional spreading resistance probe ͑SRP͒ has been widely used for this application due to its capability to measure the resistivity ͑and carrier͒ depth distribution in Si with a high geometrical resolution ͑nm͒ and high dynamic range ͑nine orders of magnitude͒. Unfortunately with the application towards very shallow profiles ͑junction depths less than 35 nm͒, the concurrent electrical resolution is influenced by several artifacts such as carrier spilling, surface damage, probe penetration, three-dimensional ͑3D͒-current spreading, increasing correction factors, etc. From the spreading resistance roadmap presented it follows that for future sub-100 nm technologies using sub-35 nm junctions, conventional SRP is reaching its limits. As the main limitations arise from the large correction factors ͑in excess of 2-3000͒ due to the large contact size and probe separation, large bevel stepsize and probe penetration, a solution is proposed, the Nanoprofiler™ ͑NP͒, which is based on a two probe version of the scanning spreading resistance microscopy SRRM technology ͑small 10-20 nm tips, low force, simultaneous topography measurement͒, thereby reducing correction factors back to Ͻ10 with minimal probe penetration and extremely small stepsize. Theoretically, profiling with 0.1-0.2 nm resolution should be feasible. In view of the complexity of controlling two independent cantilevers, we will discuss the need for them on the basis of the required correction factor size and the impact of lateral ͑3D͒-current spreading and surface damage. Some of the intrinsic capabilities of the NP concept will be illustrated by experimental resistance data measured between a single SSRM tip and TiW-Au surface stripe contact at close separation.

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Design and integration considerations for end-of-the roadmap ultrashallow junctions

Cited by 24 publications

References 16 publications

Impact of technology scaling on leakage reduction techniques

Impact of technology scaling on leakage reduction techniques

Quantitative analysis of ultrashallow junction of sub-50nm gate-length transistors: Junction depth, sheet resistance, short channel effects, and transistor performance

Spreading resistance roadmap towards and beyond the 70 nm technology node

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