Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture

Nouri, Sajjad; Ghaznavi-Youvalari, Ramin; Nurmi, Jari

doi:10.1109/norchip.2018.8573457

Cited by 2 publications

(1 citation statement)

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“…On-chip memory is incorporated to reduce the gap between memory and processor [31]. For the sine and cosine transforms which are for video coding using CGRAs, is presented in [32]. The article proposes with 4.1W power dissipation with 200 MHZ operating frequency.…”

Section: Introductionmentioning

confidence: 99%

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Dudhane¹

2020

IJETER

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In the new world of science and technology with the tremendous changes in electronic gadgets such as microprocessors and microcontrollers, becoming an important blocks of the electronics industry. For any processor, CPU has integral part which is ALU, responsible for the efficient work of the processor. This paper integrates the computing ability of 8 bit processor with 16 bit cooperative arithmetic and logic unit and 8by8 bit multiplication. In this technology, 8 bit processor keeps its ability with excellent input/ output control with maintaining its simple architecture and low power consumption. FPGA offers a platform for designing and implementing soft cores for improvement in execution time and developing IP cores. 16F84 RISC processor is designed module wise developed with HDL language and implemented using FPGA with enhanced architecture. The results are obtained in three ways as firstly designing and implementing 16 bit CALU with 8 bit processor, secondly 8by8 bit multiplier and thirdly combined integration of 16 bit CALU and 8by8 bit multiplier. Simulation result for 8 bit multiplier shows execution time of 109.241 ns, with 16 bit CALU is 674.66 ns and with multiplier and 16 bit CALU is 583.33 ns, 76.09 % cycle saving is achieved with the implementation using reconfigurable hardware, improving execution time from 674.66 ns to 583.33 ns. The design is configured on Xilinx 14.6 using FPGA and implemented using Verilog or HDL.

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Section: Introductionmentioning

confidence: 99%