In the new world of science and technology with the tremendous changes in electronic gadgets such as microprocessors and microcontrollers, becoming an important blocks of the electronics industry. For any processor, CPU has integral part which is ALU, responsible for the efficient work of the processor. This paper integrates the computing ability of 8 bit processor with 16 bit cooperative arithmetic and logic unit and 8by8 bit multiplication. In this technology, 8 bit processor keeps its ability with excellent input/ output control with maintaining its simple architecture and low power consumption. FPGA offers a platform for designing and implementing soft cores for improvement in execution time and developing IP cores. 16F84 RISC processor is designed module wise developed with HDL language and implemented using FPGA with enhanced architecture. The results are obtained in three ways as firstly designing and implementing 16 bit CALU with 8 bit processor, secondly 8by8 bit multiplier and thirdly combined integration of 16 bit CALU and 8by8 bit multiplier. Simulation result for 8 bit multiplier shows execution time of 109.241 ns, with 16 bit CALU is 674.66 ns and with multiplier and 16 bit CALU is 583.33 ns, 76.09 % cycle saving is achieved with the implementation using reconfigurable hardware, improving execution time from 674.66 ns to 583.33 ns. The design is configured on Xilinx 14.6 using FPGA and implemented using Verilog or HDL.
CPU architecture has experienced great innovation in its architecture, from 8 bit to 64 bit, CISC to RISC, Single core to multi-core and single pipelined logic to deep multi-pipelined system. Today in an era of 64 bit architectures, 8 bits are still very relevant and has not lost its position and being used in many applications. Hence this research work deals with 8 bit CPU architecture and its features enhancement to make the 8 bit case very relevant in an era of 64 bit. The co-operative ALU, as name suggests, works in tandem with existing ALU and performs 16 bits operations. The specially designed instructions shares knowledge and efficiently handles existing ALU and Co-operative ALU to perform 8 bits and 16 bits operations. The Co-operative ALU is integrated with the 2 stage pipelined 8-bit RISC architecture ensuring that existing architecture is kept intact by way of applying new functionality in the form of an extension. The reconfigurable platform software tools are used for functionality verification and final deployment is done using reconfigurable platform hardware tools.
In this paper, we have proposed the development of the Enhanced 8-bit RISC architecture and the temporal performance analysis of the enhanced architecture. The enhanced 8 bit RISC architecture is powered with the additional block called as Co-operative Arithmetic and Logical Unit (CALU). The 8 bit core is designed using FPGA as SPARTAN-6 XC65LX9-3TQG144. The purpose of designing is to integrate number of instructions with additional instructions, which are 16 bits with keeping all original instructions execution having 8 bit format. We have designed the enhanced of 8 bit processor for improvement in speed as well as to speedup of the execution cycle, so that improvement in clock cycles per second for execution of an instruction. The Enhanced RISC architecture is fully compatible with the original core along with old instruction set. The CALU is designed to enhance the multi-byte capabilities of the core. The performance improvement in terms of the clock cycle savings has been recorded. The performance enhancement of average 71% has been recorded by the Enhanced core. The Enhanced RISC core has been developed and simulated on Xilinx Vivado 2017.3.
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