Design and implementation of LT codec architecture with optimized degree distribution

Abstract

Abstract:In this paper, we present an architecture for ASIC realizations of the Luby Transform (LT) encoder and decoder. To determine the efficiency of the LT Codec architecture, the encoder and decoder are implemented with a core area of 9 mm 2 in TSMC 180-nm 1-poly 6-metal and Samsung 130-nm complementary metal-oxidesemiconductor (CMOS) technology. An empirically modified Robust Soliton degree distribution technique is applied for LT Codec implementation and its performance is analyzed in terms of chip area and cycle count. Instead of including a random generator in the register transfer level (RTL) design, we use different look-up tables (LUTs) for degree distribution, edge routing, addressing and inverse edge routing. Therefore, this architecture is efficient for hardware implementation and occupies less area inside the chip. The result shows that an area of 2.3 mm 2 is required for whole encoder and decoder implementation using TSMC library, of which 0.08 mm 2 is used for encoder implementation. Finally, a modified Robust Soliton degree distribution technique is presented and evaluated in terms of cycle count for different number of iterations using Tensilica tool. Result shows that it takes very less iterations which is more beneficial for hardware implementation of LT Codec.

Performance Analysis of LT Codec Architecture Using Different Processor Templates

“…The results of this implementation based how efficiently I will produce LT codec processor and its efficiency is calculated in terms of cycle count and time required for simulation. Area, number of gates and cells required to implement this architecture have been discussed in reference [4].…”

“…For this reason, it is very important for designers to make efficient architecture of input application and configuration files. The proposed architecture of LT codec is discussed in author's paper [4]. It is necessary one tool set for implementing application specific processors based on the TTA processor template.…”

Design and implementation of a novel LT codec architecture on TTA based codesign environment

“…The results of this implementation will show how efficiently we produced the LT codec processor, and its efficiency can be calculated in terms of cycle count and time required for simulation. Area, number of gates and cells required to implement this architecture were discussed in ref [9]. The simulation procedures using the TCE tool were also elaborately discussed in [11].…”

“…In our encoder architecture, a uniform random number generator (RNG) is applied to get the degree value from this degree distribution [9]. The address of the message signal is randomly distributed, and the combined operation of the column for degree distribution and the address of the message satisfy the distribution mentioned in the equations for ISD and RSD [8].…”

“…From the encoding explanation, we see that direct RTL mapping is more difficult than HLL mapping. At first we'll explain the ASIC architecture of LT decoder in terms Check Node Unit (CNU) and Variable Node Unit (VNU) operations [9]. Fig.…”