Design and implementation of a novel LT codec architecture on TTA based codesign environment

Abstract

Abstract:The main aim of this paper is to explain the generation technique of application specific function units (FUs) for reducing the number of instructions in Luby Transform (LT) codec processor. For this reason, Transport Triggered Architecture (TTA) is taken as an active processor template for designing a high-speed TTA-based LT codec processor using TTA-based Co-design Environment (TCE) tool. In this design, processor architectures named as P 1 , P 2 , P 3 , P 4 , P 5 , and P 6 are generated to gradually improve the performance of the TTA processor. P 6 took only 4,466 cycles and 43 ms to simulate an LT codec system. In this paper, P 6 of the TCE tool took only a single iteration to generate the decoded signal.

Performance Analysis of LT Codec Architecture Using Different Processor Templates

“…I have implemented and generated application specific processor for LT codec using Xtensa and OpenRISC processor design tools. The simulation results of TCE tool set have been shown in author's another paper in ref [6]. I have translated the complete encoding and decoding algorithm using C program.…”

“…This toolset is developed by Tampere University of Technology [5]. The comprehensive design of LT codec using TCE is elaborately explained in author's another paper [6]. Using this tool, application written in high level language can be implemented in FPGA evaluation board through RTL design flow.…”