Design and implementation of high performance architecture for packet classification

Khan, Ausaf Umar; Suryawanshi, Yogesh; Chawhan, Manish Devendra; Kakde, Sandeep

doi:10.1109/icacea.2015.7164761

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…First of all, these routers share a common architecture with varied structural composition and connection among types of router components [18][19][20][21]. Components in these routers have similar designs with some design variation.…”

Section: ) Overall Analysismentioning

confidence: 99%

Analysis and synthesis techniques of router circuits

Lee

Huang

2015

2015 4th International Conference on Computer Science and Network Technology (ICCSNT)

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Along with continuing advancement of network and chip technology, vast amount of new router designs will be designed and utilized in differentiated Internet-connected systems, on-chip interconnection in SoC, and evolving softwaredefined networks. In this research, from an analysis of current and future router designs, we observe that router designs share a common composition structure. We thus devised synthesis techniques based on the common composition structure. It allows designers specifying high-level and detailed router design decisions. Together with extensible parts of router designs organized in the common structure, it can produce desirable synthesizable Verilog router designs. We implemented the synthesis design that is based on a number of synthesis techniques and HDL configuration generation method. Experimental results show that our approach can effectively produce desirable synthesizable Verilog router designs.

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Section: ) Overall Analysismentioning

confidence: 99%

Analysis and synthesis techniques of router circuits

Lee

Huang

2015

2015 4th International Conference on Computer Science and Network Technology (ICCSNT)

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“…The memory requirement for this work is less compared to the existing FSBV approach. Khan et al [14] explain the PC module with high throughput, which uses simple XNOR gates for classifying the packets based on the ruleset. The work offers less memory utilization and low latency for the same rules used in the stride BV based PC approach.…”

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confidence: 99%

High performance modified bit-vector based packet classification module on low-cost FPGA

Anita

Devi²

2021

IJECE

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The packet classification plays a significant role in many network systems, which requires the incoming packets to be categorized into different flows and must take specific actions as per functional and application requirements. The network system speed is continuously increasing, so the demand for the packet classifier also increased. Also, the packet classifier's complexity is increased further due to multiple fields should match against a large number of rules. In this manuscript, an efficient and high performance modified bitvector (MBV) based packet classification (PC) is designed and implemented on low-cost Artix-7 FPGA. The proposed MBV based PC employs pipelined architecture, which offers low latency and high throughput for PC. The MBV based PC utilizes <2% slices, operating at 493.102 MHz, and consumes 0.1 W total power on Artix-7 FPGA. The proposed PC considers only 4 clock cycles to classify the incoming packets and provides 74.95 Gbps throughput. The comparative results in terms of hardware utilization and performance efficiency of proposed work with existing similar PC approaches are analyzed with better constraints improvement.

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Energy Efficient Routing in Vehicular Adhoc Network for Emergency Services

Bondre

Dorle

2018

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)

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Design and implementation of high performance architecture for packet classification

Cited by 3 publications

References 9 publications

Analysis and synthesis techniques of router circuits

Analysis and synthesis techniques of router circuits

High performance modified bit-vector based packet classification module on low-cost FPGA

Energy Efficient Routing in Vehicular Adhoc Network for Emergency Services

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