In this research, we designed a model expansion method that is used in a new methodology of model composition and evolution for broad design domains. In the methodology, hierarchical model compositional relationships are captured in a model composition graph (MCG) as a schema of designs. An MCG schema can be used as a blueprint for systematic and flexible evolution of designs with three hierarchical model refinement operations: expansion, synthesis, and configuration. In this research, due to the need of hierarchical sharing in software and hardware domains, we designed an algorithm to achieve conditional and recursive model expansion with hierarchical model instance sharing that is not achievable in other expansion methods. Hierarchical model instance sharing complicates the design structure from tree structures to graph structures. We thus design the model expansion algorithm with enhanced features of maintenance of MCG instance consistency, path-based search of shared submodel instances, and dependency preserving expansion ordering. The expansion specification and the expansion process are integrated with the MCG-based methodology. Model parameters set by designers and other refinement operations can be used to guide each expansion step of design models iteratively.
Along with continuing advancement of network and chip technology, vast amount of new router designs will be designed and utilized in differentiated Internet-connected systems, on-chip interconnection in SoC, and evolving softwaredefined networks. In this research, from an analysis of current and future router designs, we observe that router designs share a common composition structure. We thus devised synthesis techniques based on the common composition structure. It allows designers specifying high-level and detailed router design decisions. Together with extensible parts of router designs organized in the common structure, it can produce desirable synthesizable Verilog router designs. We implemented the synthesis design that is based on a number of synthesis techniques and HDL configuration generation method. Experimental results show that our approach can effectively produce desirable synthesizable Verilog router designs.
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