Design and Implementation of an Open Image Processing System based on NIOS II  and Altera DE2 - 70 Board

Pyrgas, Lampros; Kalantzopoulos, A.; Zigouris, E.

doi:10.25103/jestr.095.06

Cited by 2 publications

(5 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This was simulated and implemented in Xilinx Spartan 6 (XC7Z020-2CLG4841) FPGA using Verilog hardware description language. FPGAs were commonly chosen to reconfigure embedded devices [35] [36] because their implemented designs are cost-effective in contrast with using ASICs and there are no extensive modifications on software or hardware [37] [38]. Table 3 shows the resource utilization using the implementation using FPGA.…”

Section: Experimental Testing and Resultsmentioning

confidence: 99%

Overhead Interspersing of Redundancy Bits Reduction Algorithm by Enhanced Error Detection Correction Code

Tolentino¹,

Valenzuela²,

Juan³

2019

JESTR

View full text Add to dashboard Cite

Additional check bits, which are commonly attached to the message's input data, are normally used to minimize the error during data transmission. The receiver system implements a checking algorithm to determine if an error was occurred in the received data. This algorithm will correct a corrupted bit and recover the original message. An enhanced error detection correction code was presented to better detect and correct the corrupted conveyed bits. It improves the existing limitations of utilizing cyclic redundancy checking (CRC), Hamming code, and other checksum techniques. Also, it reduced the length of the redundancy bits which exists in CRC, the overhead of interspersing of the redundancy bits in a typical Hamming code, and the system resources such as processor time and bandwidth in checksum techniques. This paper was synthesized and simulated using the Xilinx Spartan 6 (XC7Z020-2CLG4841) FPGA. Results show that the resource utilization of the designed memory architecture using EEDC is lower compared to CRC, Hamming, and Checksum algorithms.

show abstract

Section: Experimental Testing and Resultsmentioning

confidence: 99%

Overhead Interspersing of Redundancy Bits Reduction Algorithm by Enhanced Error Detection Correction Code

Tolentino¹,

Valenzuela²,

Juan³

2019

JESTR

View full text Add to dashboard Cite

show abstract

“…In this article, several methods for the design of camera system architectures and applications are surveyed. The architecture design and applications examined are as follows: the implementation of a smart camera system on Xilinx VSK platform [9], the implementation of an open image processing system on the Altera DE2-70 board [8], the implementation of a smart camera on the Altera Stratix EP1S60F1020C7 device [1], the implementation of a camera system controlled from an LCD touch panel on an Altera DE2 board [14], and a real-time edge detector implementation on FPGA [15]. In Section II, the design of these architectures and the application of existing methods are discussed.…”

Section: Figure 1 Typical Block Diagram Of the Architecture Design Fomentioning

confidence: 99%

“…In [8], the author described the implementation of an open image processing system on the FPGA platform, using the Altera DE2-70 as the chosen development platform. The TRDB-D5M camera and the 4.3" Ultra-high Resolution LCD Touch Panel (TRDB-LTM) are important external peripherals completing the research.…”

Section: Literature Reviewmentioning

confidence: 99%

“…The Altera Stratix uses both SRAM and SDRAM to store video frames. Indonesian J Elec Eng & Comp Sci ISSN: 2502-4752  The selection mode display described in [8] is an extra feature that allows switching between different modes of image processing. The processing mode includes negative colour, edge detection, a median filter and a sharpen convolution filter.…”

Section: Figure 4 Block Diagram For the Architecture Design Proposed mentioning

confidence: 99%

“…The RGB conversion of captured video for further processing or storage is well-understood in video processing applications [7]. The full resolution frame rate of the TRDB-D5M Camera is up to 15 frames per second (FPS), and the image capture frame resolution is up to 2592*1944 pixels [6,8].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Implementation of a camera system using nios II on the altera DE2-70 board

Cheng

Jambek

2019

IJEECS

View full text Add to dashboard Cite

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.

show abstract

Design and Implementation of an Open Image Processing System based on NIOS II and Altera DE2 - 70 Board

Cited by 2 publications

References 3 publications

Overhead Interspersing of Redundancy Bits Reduction Algorithm by Enhanced Error Detection Correction Code

Overhead Interspersing of Redundancy Bits Reduction Algorithm by Enhanced Error Detection Correction Code

Implementation of a camera system using nios II on the altera DE2-70 board

Contact Info

Product

Resources

About