Design and implementation of a Viterbi decoder using FPGAs

Pandita, B.; Roy, Subir Kumar

doi:10.1109/icvd.1999.745223

Cited by 24 publications

(13 citation statements)

References 3 publications

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“…The codeword symbol can then be expressed as (2) where represents the th element of . Then, (1) can be written as (3) This is equivalent to the Euclidean distance between the codeword symbols and the received symbols corresponding to the branches in the original low-connectivity trellis diagram. Similar to the low-connectivity trellis decoding, in the strongly connected trellis decoding, comparisons between the path metrics are required to determine the survivor path.…”

Section: A Generation Of Composite Branch Metricsmentioning

confidence: 99%

“…In order to design and implement the modified adaptive Viterbi decoder, we choose the following specifications that have been used in [3] for hardware implementation of the Viterbi decoder: 1) constraint length: (256 states); 2) code rate: ; 3) generator polynomials: and ; 4) survivor path length:…”

Section: Design and Implementation Of Modified Adaptive Viterbi Dmentioning

confidence: 99%

“…In general, a feedback is needed in path metric updating, since the path metrics of the previous stage should be fed back to the input of an ACS processor for updating the path metric at the current stage. In the butterfly architecture-based Viterbi decoders [3]- [6], ACS computations cannot be pipelined because of the feedback that would occur between the pipeline stages. However, in the proposed systolic array-based architecture, the ACS computations can be carried out in pipeline.…”

Section: ) Adjacency Matrix Partitioning and Time Multiplexing: Formentioning

confidence: 99%

“…Some attempts have been made for low-power design of Viterbi decoders with . The field-programmable gate array (FPGA) designs of the decoders in [3] and [4], and the application-specific integrated circuit (ASIC) design of the decoder in [5] are based on a serial butterfly architecture. Another ASIC design of the decoder proposed in [6] is based on a parallel butterfly architecture with bit-serial arithmetic.…”

Section: Fpga Design and Implementation Of A Low-powermentioning

confidence: 99%

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Guo

Ahmad

Swamy

et al. 2005

IEEE Trans. Circuits Syst. I

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In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.Index Terms-Adaptive Viterbi decoder, field-programmable gate array (FPGA) implementation, low-power design, systolic array architecture.

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Section: A Generation Of Composite Branch Metricsmentioning

confidence: 99%

Section: Design and Implementation Of Modified Adaptive Viterbi Dmentioning

confidence: 99%

Section: ) Adjacency Matrix Partitioning and Time Multiplexing: Formentioning

confidence: 99%

Section: Fpga Design and Implementation Of A Low-powermentioning

confidence: 99%

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Guo

Ahmad

Swamy

et al. 2005

IEEE Trans. Circuits Syst. I

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“…The decoding complexity of the viterbi decoder increases with respect to the code length.However, to counteract the exponential dependence of Viterbi decoder complexity on higher memory order in low-power designs; good power reduction methods are needed. In order to overcome this problem, the adaptive Viterbi Decoder (A VD) [4] [11] has been developed. This Decoder reduces the average number of computations required per bit of decoded infonnation while achieving comparable bit error rates (BER) versus Viterbi algorithm implementations.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Radix2 ACS in Adaptive Viterbi decoder

Bobby¹,

Srivatsa

Lalkishore

2011

International Conference on Nanoscience, Engineering and Technology (ICONSET 2011)

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Adaptive viterbi decoder is used for decoding codes of long constraint length, Where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, we have implemented Radix 2 ACS in viterbi decoder and Adaptive Viterbi decoder. The area consumption was less in viterbi compared to Adaptive Viterbi decoder. But the power utilization reduced drastically to 20%where as in Viterbi decoder the power consumed was 80%. In our previous work we have implemented Adaptive fast ACS, but the experimental result proves power consumption is less in radix 2 ACS in viterbi decoder and much less in Adaptive viterbi decoder.

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