Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Qui, Nguyen My; Lin, Chang Hong; Chen, Poki

doi:10.1109/access.2020.3024851

Cited by 11 publications

(3 citation statements)

References 15 publications

(16 reference statements)

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“…The control problems of the tongue control system mainly focus on power loss and control accuracy issues. Currently, popular tongue control research protocols include the low-power independent system of tongue drive (iSTD) based on the magnetic array, extraoral tongue drive system (ETDS), and joystick-controlled tongue control intelligent assistive device (STD) [3][4][5]. For iSTD systems, any bumps on a wheelchair of the patient may lead to the misoperation of magnetic beads on the tongue and cause the control unit to emit misoperation signals, and ETDS and STD sometimes have similar problems.…”

Section: Relevant Workmentioning

confidence: 99%

Non-Invasive Intraoral Stand-Alone Tongue Control System Based on RSIC-V Edge Computing

Shi,

Peng,

Zhao

et al. 2023

Applied Sciences

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The intelligent tongue control system is of great significance for assisting the independent life of patients with a limb disability. In order to more accurately control the assisted living equipment of incompetent patients and solve the power-loss problem of the intelligent tongue control system, this research designs a non-invasive pressure sensor array for tongue touch signal detection in the oral cavity and proposes a tongue control system based on RSIC-V edge computing. The system converts the tongue touch pressure data into specific control instructions on the edge of the RSIC-V chip and transmits them to the receiver, thus reducing the transmission of data. This study takes control of the wheelchair motor as the test object. In the experiment, the speed response time test, the center click task, and the power consumption experiment are carried out, whose results show that the adaptive fuzzy PID control algorithm has good robustness in the system; when the DC motor with a given speed of 750 r/min reaches the steady state, its rise time is 0.108 s and the adjustment time is 0.59 s. The dynamic power consumption of the non-intrusive intraoral stand-alone tongue control system proposed in this paper is found to be 3.745 MW, which is 11.5% lower than the total power consumption of the sTD system.

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Section: Relevant Workmentioning

confidence: 99%

Non-Invasive Intraoral Stand-Alone Tongue Control System Based on RSIC-V Edge Computing

Shi,

Peng,

Zhao

et al. 2023

Applied Sciences

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“…The master MCU performs the local gateway computing there by the IoT system, saves the bandwidth costs, and reduces the communication response time between multiple devices. Here the gateway is realized by combining the multi-MCU design with a field-programmable gate array (FPGA) [14]. Increasing the data processing abilities of the cloud server does not shell out an increase in network latency.…”

Section: B Background On Iot Socmentioning

confidence: 99%

Systematic Approach for State-of-the-Art Architectures and System-on-Chip Selection for Heterogeneous IoT Applications

et al. 2021

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The Internet of Things (IoT) refers to a network of physical devices, which collects data and processes into a system without human intervention. In the commercialized market, IoT architectures are upgrading day by day to reduce data transmission costs, latency, and bandwidth usage for various application requirements. The extensively available IoT architectures and their specification resist the researchers to select a system-on-chip (SoC) for heterogeneous IoT applications. This paper seeks to comprehend the various IoT device specifications and their characteristics to support multiple applications. Moreover, microprocessor architectures and their components are detailed to facilitate developer knowledge in advanced methodology and technology. The various instructions set architectures (ISA) are implemented in a Zynq-7000 (xc7Zz20clg484-1) FPGA device to examine the feasibility of design space requirements for real-time hardware execution. To select specific system-on-chip (SoC) architecture for heterogeneous IoT applications, a genetic algorithm (GA) based optimization method is implemented in MATLAB. The proposed algorithm identifies the optimized SoC architecture concerning device parameters such as a clock, cache, RAM space, external storage, network support, etc. Further, the confusion matrix method evaluates the proposed algorithm's accuracy, which yields 84.62% accuracy. The outcome of SoCs attained through the GA are tested by analyzing their execution time and performance using various evaluation benchmarks. This article helps the researchers and field engineers to comprehend the microarchitecture device configurations and to identify the superior SoC for next-generation IoT practices.INDEX TERMS Internet of Things, Microprocessors, System-on-chip, Heterogeneous Architectures, and Edge Computing.

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“…This instruction set can be widely extended adding ad-hoc instructions and customized even using commercial tool-chains engineered with leading compiler infrastructures. This notwithstanding, in general, the number of resources used to implement speed-focused RV32I microarchitectures is still considerable (see [22], [23]) assuming aggressive low-area requirements. With minimal synthesized features, for an RV32I the number of LUTs FF and memory elements required is on the order of 0.9 k, 0.4 k, and 1 k on an Intel Cyclone-IV FPGA [21].…”

Section: Introductionmentioning

confidence: 99%

A Multi-One Instruction Set Computer for Microcontroller Applications

2021

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This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes (mOISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of mOISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8 bit I/O register, and 64 kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer's demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of mOISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang. Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating mOISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I 2 C) temperature sensor, using its 8 bit I/O port, with software bus interface implementation. mOISC occupies ∼6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized mOISC is 12 mA at 100 MHz clock.

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Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Cited by 11 publications

References 15 publications

Non-Invasive Intraoral Stand-Alone Tongue Control System Based on RSIC-V Edge Computing

Non-Invasive Intraoral Stand-Alone Tongue Control System Based on RSIC-V Edge Computing

Systematic Approach for State-of-the-Art Architectures and System-on-Chip Selection for Heterogeneous IoT Applications

A Multi-One Instruction Set Computer for Microcontroller Applications

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