Design and implementation of a new efficient median filtering algorithm

Hiasat, A.A.; Al-Ibrahim, M.M.; Gharaibeh, Khaled M.

doi:10.1049/ip-vis:19990444

Cited by 21 publications

(12 citation statements)

References 7 publications

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“…Being narrow, the filter ends up filtering part of the signal. Some work was been done to improve numerical differentiation in signals [6,10,11] including the angular velocity [10]. Our goal is to propose an alternative method that allows the implementation to be simple and that can be implemented in real-time.…”

Section: Measurement Using An Encodermentioning

confidence: 99%

Real time angular velocity measure using median filter

Martins¹,

Dias²,

Queiroz

2013

Proceeding Series of the Brazilian Society of Computational and Applied Mathematics

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Abstract⎯We present a simple approach to reduce the noise present in velocity measurements when using encoders. The approach is to use the median filter together with a simple first order linear filter and show that this combination avoids the errors due to warp of the encoder (when the angle goes from 2π back to 0 of vice versa). We test this new method and compare with different kinds of filters and algorithms to avoid the warp problem. We show that the proposed method can be implemented only with simple arithmetic and is perfectly suitable for embedded and hardware implementation.

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Section: Measurement Using An Encodermentioning

confidence: 99%

Real time angular velocity measure using median filter

Martins¹,

Dias²,

Queiroz

2013

Proceeding Series of the Brazilian Society of Computational and Applied Mathematics

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“…A compact majority voting circuit using an adder array to count the number of 1s and a threshold comparator to determine an individual bit of the median is described by Benkrid et al [7]. Variations on this approach have been described in the literature [107][108][109]. Systolic array architectures for bit-level sorting networks have been shown to improve concurrency of the bit-serial sorting designs [102,103,[110][111][112][113].…”

Section: Multiobjective Optimizationmentioning

confidence: 99%

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

Dandekar¹

2008

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Minimally invasive image-guided interventions (IGIs) are time and cost efficient, minimize unintended damage to healthy tissues, and lead to faster patient recovery. Advanced three-dimensional (3D) image processing is a critical need for navigation during IGIs. However, achieving on-demand performance, as required by IGIs, for these image processing operations using software-only implementations is challenging because of the sheer size of the 3D images, and memory and compute intensive nature of the operations. This dissertation, therefore, is geared toward developing high-performance 3D image processing architectures, which will enable improved intraprocedural visualization and navigation capabilities during IGIs.In this dissertation we present an architecture for real-time implementation of 3D filtering operations that are commonly employed for preprocessing of medical images. This architecture is approximately two orders of magnitude faster than corresponding software implementations and is capable of processing 3D medical images at their acquisition speeds. Report Documentation PageCombining complementary information through registration between pre-and intraprocedural images is a fundamental need in the IGI workflow. Intensity-based deformable registration, which is completely automatic and locally accurate, is a promising approach to achieve this alignment. These algorithms, however, are extremely compute intensive, which has prevented their clinical use. We present an FPGA-based architecture for accelerated implementation of intensity-based deformable image registration. This high-performance architecture achieves over an order of magnitude speedup when compared with a corresponding software implementation and reduces the execution time of deformable registration from hours to minutes while offering comparable image registration accuracy.Furthermore, we present a framework for multiobjective optimization of finite-precision implementations of signal processing algorithms that takes into account multiple conflicting objectives such as implementation accuracy and hardware resource consumption. The evaluation that we have performed in the context of FPGA-based image registration demonstrates that such an analysis can be used to enhance automated hardware design processes, and efficiently identify a system configuration that meets given design constraints. In addition, we also outline two novel clinical applications that can directly benefit from these developments and demonstrate the feasibility of our approach in the context of these applications. These advances will ultimately enable integration of 3D image processing into clinical workflow.

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“…Many approaches for hardware implementation of rank-order filtering have been presented in the past decades [8,[10][11][12][13][14][15][16][17][18][19][20][21][22][23][24]. Many of them are based on sorting algorithm [11,22,23,[25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

“…The proposed approach significantly reduce the area complexity from exponential to linear. Papers [10,13,[16][17][18]21,33,34] employ the bit-sliced majority algorithm for median filtering, the most popular type of rank-order filtering. The bit-sliced algorithm [36,37] bitwisely selects the ranked candidates and generates the ranked result one bit at a time.…”

Section: Introductionmentioning

confidence: 99%

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On VLSI design of rank-order filtering using DCRAM architecture

Lin

Dung

2008

Integration

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This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for realtime speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm 2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

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Design and implementation of a new efficient median filtering algorithm

Cited by 21 publications

References 7 publications

Real time angular velocity measure using median filter

Real time angular velocity measure using median filter

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

On VLSI design of rank-order filtering using DCRAM architecture

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