Design and hardware implementation of Look-Up Table predistortion on ALTERA stratix DSP board

Alasady, H.; Ibnkahla, Mohamed

doi:10.1109/ccece.2008.4564799

Cited by 8 publications

(6 citation statements)

References 6 publications

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“…and focuses also on the approaches of creating VHDL model of CDMA transmitter by Mohamed, et al [61]. In addition, Alasady and Ibnkahla [62] offered the design technique and implementation results of a 16-QAM lookup table pre-distortion system for satellite communications by Altera DSP board. And, Tuan and Araki [63] proposed the adaptive modulation to increase the throughput of a wireless network using regulating the modulation structure of the channel station.…”

Section: B the Development Of Designs For Wireless Communication Sysmentioning

confidence: 99%

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Nahar¹,

Gitaffa²,

Ali³

et al. 2017

Review of Information Engineering and Applications

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Software Defined Radio (SDR) has the flexibility to modify the characteristics of the receiving and transmitting radio device, without physically adjusting the hardware, due to development in the system. Because of the increasing need for wireless communication applications so as to enable consumers to communicate anywhere through information led to the emergence of many communication devices to include the large amount of applications that every one of the devices needs power and thereby increase the total power. This study confirms that the wireless communication system for secured transmit data, fast and inexpensive; can be done by implementing using Partial Reconfiguration (PR) modern technology in FPGA developing based on SDR. The Speed and performance can be improved. The area also can be decreased. The new Xilinx, Vertex Series FPGA, provides the provision of PR. The power consumption can be reduced by applying power reduction techniques in the blocks. The combination of MATLAB (Simulink and M-file) and Simulink HDL Coder offers flexible capabilities for analysis, design; simulation, implementation, and verification. With all these capabilities, in a single system to reduce the time spent tuning for reducing the algorithms and models during rapid prototyping and experimentation and less time on HDL coding. Contribution/ Originality: This study contributes in the existing literature review for implementing MC-CDMA wireless communication system using Partial Reconfiguration (PR) that is a new technology in FPGA. 1. INTRODUCTION The wireless communications revolution started with the mobile phone at the beginning of the 80's and all the improvements which have led to the multiplication of mobile and wireless communications networks and standards [1]. The 1st Generation (1G) of technology was characterized by analog means voice only; 1G quality was too low and also had connections to low speed, but they effectively offered the inherent easiness of mobile communications. The system used in 1G was Frequency Division Multiple Access (FDMA) [2]. The 2nd Generation (2G) of technology is digital in the United States, most of the devices and services were digital. The spread of digital mobile

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Section: B the Development Of Designs For Wireless Communication Sysmentioning

confidence: 99%

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Nahar¹,

Gitaffa²,

Ali³

et al. 2017

Review of Information Engineering and Applications

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“…Different non-radiation hardened FPGA families are compared against various crucial parameters like the available logic resources, transceivers, Phase lock loops (PLL) and market availability for the choice of FPGA chip on DPU as listed in the table 4. Intel Stratix-V GX FPGA [23] has been chosen due to the enough available resources as per the requirement of prototype tests.…”

Section: Costmentioning

confidence: 99%

A potent approach for the development of FPGA based DAQ system for HEP experiments

et al. 2017

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With ever increasing particle beam energies and interaction rates in modern High Energy Physics (HEP) experiments in the present and future accelerator facilities, there has always been the demand for robust Data Acquisition (DAQ) schemes which perform in the harsh radiation environment and handle high data volume. The scheme is required to be flexible enough to adapt to the demands of future detector and electronics upgrades, and at the same time keeping the cost factor in mind. To address these challenges, in the present work, we discuss an efficient DAQ scheme for error resilient, high speed data communication on commercially available state-of-the-art FPGA with optical links. The scheme utilises GigaBit Transceiver (GBT) protocol to establish radiation tolerant communication link between on-detector front-end electronics situated in harsh radiation environment to the back-end Data Processing Unit (DPU) placed in a low radiation zone. The acquired data are reconstructed in DPU which reduces the data volume significantly, and then transmitted to the computing farms through high speed optical links using 10 Gigabit Ethernet (10GbE). In this study, we focus on implementation and testing of GBT protocol and 10GbE links on an Intel FPGA. Results of the measurements of resource utilisation, critical path delays, signal integrity, eye diagram and Bit Error Rate (BER) are presented, which are the indicators for efficient system performance.

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“…There are some works related to hardware implementation based on DSP tools (Alasady and Ibnkahla, 2008;Xiong et al, 2008) and others applied to control systems (Bin and Run-lin, 2011). The MPM used in this approach as a design tool allows to easily model memory and nonlinear effects and, moreover, to clearly identify the generated data in the digital to analog converter (DAC) located in the high-speed mezzanine card (HSMC) included in the mentioned DSP board.…”

Section: Pa Conversions and Mpm Implementation On A Dsp/fpga Boardmentioning

confidence: 99%

Flexible test bed for the behavioural modelling of power amplifiers

Nuñez-Perez

Cárdenas-Valdez

Gontrand

et al. 2013

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose -The paper aims to focus on the memory-polynomial model (MPM) as special case of Volterra series, implemented in hardware. The behavior of the MPM is fully proved through a comparison with AM-AM and AM-PM measured data. The results show that this simulation technique is able to prove the effectiveness of the MPM implementation as behavioural model for high power radiofrequency amplifiers. The system is able to compensate perturbations caused by modern communication systems. Design/methodology/approach -The implementation uses Matlab-Simulink, and its digital signal processing (DSP) builder. The first stage allows developing the model in Matlab using the DSP builder blockset through the signal compiler block. Then, the design is downloaded to the DSP board. Findings -The paper demonstrates a proper behavior of the MPM as a truncation of the Volterra series, with respect to different inputs. This is a key point, because the series truncations allow first to implement this model in real time and second to obtain a correct precision, for instance when modeling amplification of digital signals in high frequency. Originality/value -The global system approach permits to easily develop, simulate, and validate a wireless system. The efficiency of a complete connected solution based on Agilent Technologies tools, combining simulations and measurements under true operating conditions, seems to be clearly demonstrated.

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Design and hardware implementation of Look-Up Table predistortion on ALTERA stratix DSP board

Cited by 8 publications

References 6 publications

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

A potent approach for the development of FPGA based DAQ system for HEP experiments

Flexible test bed for the behavioural modelling of power amplifiers

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