Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal–oxide–semiconductor–molecular circuits

Masoumi, Massoud; Raissi, Farshid; Ahmadian, M.; Keshavarzi, Parviz

doi:10.1088/0957-4484/17/1/015

Cited by 26 publications

(9 citation statements)

References 20 publications

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“…The challenge is to implement correlationbased learning laws, such as STDP [4], based on the state of a two-terminal nanodevice for long-term potentiation (LTP) (for pre-before-postsynaptic spiking) and long-term depression (LTD) (for post-before-presynaptic spiking) as well as state storage. Conventional CMOL circuits [1,5] comprise bistable single-electron devices (SEDs) whose behavior are like single bit Resistance-change RAMs (ReRAMs). But, the resistance of recently fabricated nanodevice, 'memristive' [6], is nonlinear and varying between "On" (low resistance) state and "Off" (high resistance) state by applying appropriate voltages.…”

Section: Introductionmentioning

confidence: 99%

STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks

Afifi

Ayatollahi

Raissi

2009

IEICE Electron. Express

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Implementation of a correlation-based learning rule, SpikeTiming-Dependent-Plasticity (STDP), for asynchronous neuromorphic networks is demonstrated using 'memristive' nanodevice. STDP is performed using locally available information at the specific moment of time, for which mapping to crossbar-based CMOS-Nano architectures, such as CMOS-MOLecular (CMOL), is done rather easily. The learning method is dynamic and online in which the synaptic weights are modified based on neural activity. The performance of the proposed method is analyzed for specifically shaped spikes and simulation results are provided for a synapse with STDP properties.

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Section: Introductionmentioning

confidence: 99%

STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks

Afifi

Ayatollahi

Raissi

2009

IEICE Electron. Express

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“…The results implied that CMOL FPGA may provide area-delay advantage beyond two orders of magnitude over purely CMOS FPGA circuits, at manageable power consumption, simultaneously with high defect tolerance (above 20% of bad nanodevices). Later, an almost similar density advantage was reported for CMOL FPGA implementation of an advanced encryption algorithm [22]. However, these results were still insufficient to evaluate the benefits of the CMOL FPGA concept for general-purpose computing.…”

mentioning

confidence: 69%

A reconfigurable architecture for hybrid CMOS/Nanodevice circuits

Strukov

Likharev

2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

125

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This report describes a preliminary evaluation of performance of a cell-FPGA-like architecture for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack and a two-level nanowire crossbar with molecular-scale two-terminal nanodevices (programmable diodes) formed at each crosspoint. Our cell-based architecture is based on a uniform CMOL fabric of "tiles". Each tile consists of 12 four-transistor basic cells and one (four times larger) latch cell. Due to high density of nanodevices, which may be used for both logic and routing functions, CMOL FPGA may be reconfigured around defective nanodevices to provide high defect tolerance. Using a semicustom set of design automation tools we have evaluated CMOL FPGA performance for the Toronto 20 benchmark set, so far without optimization of several parameters including the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide a density advantage of more than two orders of magnitude over the traditional CMOS FPGA with the same CMOS design rules, at comparable time delay, acceptable power consumption and potentially high defect tolerance.

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“…Moreover CMOL circuits have another advantage in comparison with regular CMOS circuits and are inherently defect tolerant [12], [13]. We have recently shown that basic modules of Rijndael can be implemented by CMOL technology with very interesting results [16]. The results we have obtained demonstrate that longer keys can be easily realized by CMOL, making unauthorized deciphering almost impossible.…”

Section: Introductionmentioning

confidence: 89%

NanoCMOS-Molecular Realization of Rijndael

Masoumi

Raissi

Ahmadian

2006

Lecture Notes in Computer Science

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Abstract. This paper describes the implementation of the Advanced Encryption Standard Algorithm, Rijndael, in a new nanoscale technology, called CMOL. This technology consists of an array of conventional CMOS gates and a wiring network, which consists of a high density mesh of nanowires. The basic Modules of Rijndael were implemented using CMOL architecture. It is observed that the implementation in such a technology has considerable advantages compared to a conventional CMOS approach as regards to defect tolerance, speed, area and power consumption.

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Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal–oxide–semiconductor–molecular circuits

Cited by 26 publications

References 20 publications

STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks

STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks

A reconfigurable architecture for hybrid CMOS/Nanodevice circuits

NanoCMOS-Molecular Realization of Rijndael

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