A reconfigurable architecture for hybrid CMOS/Nanodevice circuits

Abstract

This report describes a preliminary evaluation of performance of a cell-FPGA-like architecture for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack and a two-level nanowire crossbar with molecular-scale two-terminal nanodevices (programmable diodes) formed at each crosspoint. Our cell-based architecture is based on a uniform CMOL fabric of "tiles". Each tile consists of 12 four-transistor basic cells and one (four times larger) latch cell. Due to high density of nanodevices, which may be used for both logic and routing functions, CMOL FPGA may be reconfigured around defective nanodevices to provide high defect tolerance. Using a semicustom set of design automation tools we have evaluated CMOL FPGA performance for the Toronto 20 benchmark set, so far without optimization of several parameters including the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide a density advantage of more than two orders of magnitude over the traditional CMOS FPGA with the same CMOS design rules, at comparable time delay, acceptable power consumption and potentially high defect tolerance.

FPGA Architecture: Survey and Challenges

“…Connecting the wired-OR to the CMOS inverter restores the voltage levels and also makes the design functionally complete. This approach yielded improvements in density of on average 110 times compared to 45 nm CMOS [191]. However, the speed estimates indicate the design is considerably (5X) slower than the CMOS implementation [191].…”

“…An alternative architecture, called the CMOL FPGA, shifts more of the functionality to the nanodevices [190,191]. Implementing LUTbased logic with these nanodevices is not efficient [190] and, therefore, a PLA-based approach is used.…”

CMOL: Second life for silicon?

“…Still, the areadelay product compares very favorably with the estimated 70,000 ns-µm 2 (with 1.7 ns delay and 39,000 µm 2 area) for a fully CMOS FPGA implementation of the same circuit (with the same F CMOS ). Very recently, these calculations were extended [26] to all 20 circuits of the so-called Toronto benchmark set [27]. In order to accomplish this task, the first CMOL CAD tool has been developed using a combination of known CMOS FPGA design algorithms such as SIS, TVPack and VPR [28,29] with a CMOL-specific, custom routing program.…”

NanoCMOS-Molecular Realization of Rijndael

“…Indeed, we first map the original pre-optimized logic circuit onto a network of NOR gates (with a certain maximum fan-in) and latches (if any), to produce a netlist. Next, we fix a certain number (N) of CMOS cells inside each tile to perform logic operations, while the rest T−N CMOS cells are committed to routing [18]. …”