Design and evaluation of a high throughput robust router for network-on-chip

Alhussien, Abdulaziz; Wang, Chifeng; Bagherzadeh, Nader

doi:10.1049/iet-cdt.2011.0082

Cited by 9 publications

(15 citation statements)

References 19 publications

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“…The results indicate that the proposed 3D router is characterized by the best leakage power consumption with a reduction of about 76.3% relatively to [17]. Dynamic power www.ijacsa.thesai.org consumption wise, the proposed router outperforms the 2D router of [17] with a reduction of about 28.8%.…”

Section: B Asic Based Designmentioning

confidence: 92%

“…Dynamic power www.ijacsa.thesai.org consumption wise, the proposed router outperforms the 2D router of [17] with a reduction of about 28.8%. The augmentation relative to the 3D router of [18] is only about 15.06%.…”

Section: B Asic Based Designmentioning

confidence: 95%

“…Their router implements Elevator-First routing algorithm that avoids deadlocks by using only two virtual channels in the plane. The results show that in terms of area, the proposed 3D router is 18.27 and 14.33 times smaller than the router of [17] and [18], respectively.…”

Section: B Asic Based Designmentioning

confidence: 96%

“…Compared to the 2D router, the 3D router shows a augmentation of about 2.2 times for area, and about 2.53 times for power, due to the additional hardware requirements of the 3D router. Table 7 illustrates a comparison in terms of area and power consumption of the proposed 3D router with two other routers presented in [17] and [18]. Our choice has been fixed on these routers due to their remarkable performance.…”

Section: B Asic Based Designmentioning

confidence: 99%

“…Our choice has been fixed on these routers due to their remarkable performance. The authors of [17] describe robust router architecture that implements an adaptive routing algorithm ensuring fault tolerance both in router components and network links. It also provides high throughput by avoiding deadlocks without any use of virtual channels.…”

Section: B Asic Based Designmentioning

confidence: 99%

See 4 more Smart Citations

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

Chemli¹,

Zitouni²,

Coelho³

et al. 2017

ijacsa

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Abstract-As a relevant communication structure for integrated circuits, Network-on-Chip (NoC) architecture has attracted a range of research topics. Compared to conventional bus technology, NoC provides higher scalability and enhances the system performance for future System-on-Chip (SoC). Divergently, we presented the packet-switching router design for 2D NoC which supports 2D mesh topology. Despite the offered benefits compared to conventional bus technology, NoC architecture faces some limitations such as high cost communication, high power consumption and inefficient router pipeline usage. One of the proposed solutions is 3D design. In this context, we suggest router architecture for 3D mesh NoC, a natural extension of our prior 2D router design. The proposal uses the wormhole switching and employs the turn mod negativefirst routing algorithm Thus, deadlocks are avoided and dynamic arbiter are implemented to deal with the Quality of Service (QoS) expected by the network. We also adduce an optimization technique for the router pipeline stages. We prototyped the proposal on FPGA and synthesized under Synopsys tool using the 28 nm technology. Results are delivered and compared with other famous works in terms of maximal clock frequency, area, power consumption and estimated peak performance.

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Section: B Asic Based Designmentioning

confidence: 92%

Section: B Asic Based Designmentioning

confidence: 95%

Section: B Asic Based Designmentioning

confidence: 96%

Section: B Asic Based Designmentioning

confidence: 99%

Section: B Asic Based Designmentioning

confidence: 99%

See 3 more Smart Citations

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

Chemli¹,

Zitouni²,

Coelho³

et al. 2017

ijacsa

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An Overview of Multicast Routing Algorithms in Network on Chip

Velayudham¹,

Rajagopal

Kathirvel³

et al. 2021

Learning and Analytics in Intelligent Systems

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Fine-Grained Fault-Tolerant Adaptive Routing for Networks-on-Chip

Liu

Harkin

Maguire

et al. 2015

Algorithms and Architectures for Parallel Processing

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Wireless sensor networks have become incredibly popular due to the Internet of Things' (IoT) rapid development. IoT routing is the basis for the efficient operation of the perception-layer network. As a popular type of machine learning, reinforcement learning techniques have gained significant attention due to their successful application in the field of network communication. In the traditional Routing Protocol for lowpower and Lossy Networks (RPL) protocol, to solve the fairness of control message transmission between IoT terminals, a fair broadcast suppression mechanism, or Drizzle algorithm, is usually used, but the Drizzle algorithm cannot allocate priority. Moreover, the Drizzle algorithm keeps changing its redundant constant k value but never converges to the optimal value of k. To address this problem, this paper uses a combination based on reinforcement learning (RL) and trickle timer. This paper proposes an RL Intelligent Adaptive Trickle-Timer Algorithm (RLATT) for routing optimization of the IoT awareness layer. RLATT has triple-optimized the trickle timer algorithm. To verify the algorithm's effectiveness, the simulation is carried out on Contiki operating system and compared with the standard trickling timer and Drizzle algorithm. Experiments show that the proposed algorithm performs better in terms of packet delivery ratio (PDR), power consumption, network convergence time, and total control cost ratio.

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Design and evaluation of a high throughput robust router for network-on-chip

Cited by 9 publications

References 19 publications

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

An Overview of Multicast Routing Algorithms in Network on Chip

Fine-Grained Fault-Tolerant Adaptive Routing for Networks-on-Chip

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