Design and Development of Encapsulation Process for CIS-TSV Wafer Level Package

Zhou, Tianshen; Hang, Tao; Ma, Shuying; Xiang, Min

doi:10.1109/icept50128.2020.9202872

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5d Integration1

A Via-last Process1

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2022

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Cited by 1 publication

(2 citation statements)

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“…The Si photonics wafers in this work were fabricated in a commercial Si photonics foundry followed by a via-last TSV process [18][19][20][21][22][23], C4 bumping [24], die attach and wafer dicing JSTQE-INV-PECATP2023-09417-2022.R1, accepted 10 Oct 2022.…”

Section: 5d Integrationmentioning

confidence: 99%

See 1 more Smart Citation

2.5D Heterogeneous Integration for Silicon Photonics Engines in Optical Transceivers

Nagarajan

Liu

Coccioli

et al. 2022

IEEE J. Select. Topics Quantum Electron.

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We present our work in the area of heterogeneous optical integration, where separately manufactured electronic components are assembled on to an active silicon photonics interposer to form a higher-level component. This process allows for the integration of components independently designed and optimized from several different technology and foundry platforms onto a common interposer. Heterogeneous integration is essential for manufacturing higher speed and performance components. Higher levels of integration also allow for closer placement of devices which minimizes the parasitic power consumed to compensate for the frequency dependent losses in the interconnect traces.

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Section: 5d Integrationmentioning

confidence: 99%

“…The completed silicon photonics wafer is first thinned and the TSV's are formed using a "via-last" process. Next a Re-Distribution Layer (RDL) [22] and C4 bumps are fabricated on the bottom side of the wafer. The wafer is then ready for front side die attach.…”

Section: A Via-last Processmentioning

confidence: 99%