Design and Development of Efficient Face Recognition Architecture Using Neural Network on FPGA

Ahmed, Mourad; Sinha, Samarth

doi:10.1109/iccons.2018.8663098

Cited by 5 publications

(1 citation statement)

References 16 publications

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“…Bonny et al [ 45 ] implemented a histogram-based face recognition method on a Zynq-7000 FPGA using

-pixel images, with less than 20% resource utilization and a throughput of one face identification per second with a 100 MHz clock. Ahmed et al [ 46 ] proposed a neural network (NN) classifier using features based on a histogram of oriented gradients (HOG). They implemented the algorithm on a Xilinx Virtex-7 FPGA with a 157 MHz clock, and they report 90% accuracy with

-pixel images at native video frame rate.…”

Section: Related Workmentioning

confidence: 99%

Face Recognition on a Smart Image Sensor Using Local Gradients

Valenzuela

Soto

Zarkesh-Ha

et al. 2021

Sensors

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In this paper, we present the architecture of a smart imaging sensor (SIS) for face recognition, based on a custom-design smart pixel capable of computing local spatial gradients in the analog domain, and a digital coprocessor that performs image classification. The SIS uses spatial gradients to compute a lightweight version of local binary patterns (LBP), which we term ringed LBP (RLBP). Our face recognition method, which is based on Ahonen’s algorithm, operates in three stages: (1) it extracts local image features using RLBP, (2) it computes a feature vector using RLBP histograms, (3) it projects the vector onto a subspace that maximizes class separation and classifies the image using a nearest neighbor criterion. We designed the smart pixel using the TSMC 0.35 μm mixed-signal CMOS process, and evaluated its performance using postlayout parasitic extraction. We also designed and implemented the digital coprocessor on a Xilinx XC7Z020 field-programmable gate array. The smart pixel achieves a fill factor of 34% on the 0.35 μm process and 76% on a 0.18 μm process with 32 μm × 32 μm pixels. The pixel array operates at up to 556 frames per second. The digital coprocessor achieves 96.5% classification accuracy on a database of infrared face images, can classify a 150×80-pixel image in 94 μs, and consumes 71 mW of power.

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“…Bonny et al [ 45 ] implemented a histogram-based face recognition method on a Zynq-7000 FPGA using

-pixel images at native video frame rate.…”

Section: Related Workmentioning

confidence: 99%