Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

Ogura, S.; Tsang, P. J.; Walker, William W.; Critchlow, D.L.; Shepard, J.

doi:10.1109/jssc.1980.1051416

Cited by 58 publications

(31 citation statements)

References 13 publications

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“…The turnon characteristics of these devices at 0.5-to 4-,m channel length have been extensively studied to develop the two-dimensional charge-sharing mechanism in buried-channel transistors. The dependence of V, on gate length for both buried-channel MOSFETs and MESFET devices is 49 …”

Section: Double Charge-sharing Effectmentioning

confidence: 99%

Verify and Extend VLSI Device Models

Leiss¹,

Yang²,

Chatterjee³

et al. 1982

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Section: Double Charge-sharing Effectmentioning

confidence: 99%

Verify and Extend VLSI Device Models

Leiss¹,

Yang²,

Chatterjee³

et al. 1982

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“…Many candidates of possible high-k gate dielectrics have been suggested to replace SiO 2 and they include nitride Si 3 N 4 , Hf-based oxides, and Zr-based oxides. Hf-based oxides have been recently highlighted as the most suitable dielectric materials because of their comprehensive performance in order to continue manufacturing low-cost semiconductor products, its dimension and concentration, like oxide thickness and substrate profile and device structure [6][7]28].…”

Section: Introductionmentioning

confidence: 99%

Scrutiny of Leakage Currents with Insulating Materials for Transistor Applications

Ullah¹,

Fouad²

2018

IJMSA

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Continuous reducing the size of transistor technology has enabled extraordinary improvements in the switching speed, density, functionality and cost of microprocessors. Integrated Circuit industry is pursuing Moore's curve down to deepnanoscale dimensions. Advanced transistor technology now faces many challenges that together result in static power consumption due to leakage currents. In fact, leakage currents are responsible for more than 50% of the total power consumption in nanoscale designs. In deep-nanoscale arena, this percentage will increase further. However, diagnosing of the interface quality and interaction between insulators and semiconductors is significant to reduce the leakage current and achieve the high performance of switching devices in the nanoscale domain. Continuous scaling down has required drastic decreases of the SiO 2 dielectric film thickness to achieve ever-higher capacitance densities. Fundamental limits of SiO 2 as a dielectric material, imposed by electron tunneling, will be reached as this SiO 2 film thickness approaches ~1nm. Therefore, alternate high-k interlayer dielectric material will be needed to replace SiO 2 as a capacitor and gate dielectric material. Numerous alternate high-k materials are being actively investigated, ranging from Al 2 O 3 (k ~ 9) to HfO 2 (k ~ 25). High-k materials hold the promise of achieving very high capacitance densities with relatively thick films. His research interests includes a relatively new methodology and nanotechnology for the next generation of computing and other micro-and nano-electronic applications. Emadelden Fouad received his B. Sc and M. Sc degree with Theoretical Physics from Cairo University, Egypt in 1996 and 2001 respectively. Emadelden also finished his PhD with theoretical Nano device from Cairo University, Egypt in 2005. Previously he worked as a teaching assistant, and instructor with the department of Physics at Cairo University. Currently he is working as an assistant professor of physics with the department of natural science at Florida Polytechnic University. His research interest include but not limited to quantum transport characteristics of energy efficient devices, Electromagnetic properties of type II superconductors and emerging nanomaterials like graphene.

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“…In this paper, two 50nm asymmetric MOSFETs are designed. One with LDD (lightly doped drain) [4] structure at drain only and other having unequal junction depths. These structures are designed and simulated using device simulator SILVACO in the nanometer regime.…”

Section: Introductionmentioning

confidence: 99%

Design styles of Asymmetric nMOS and their Simulation

Ramesh¹

2015

IJRITCC

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Abstract-Scaling down of the MOSFET has been done extensively to meet the need for high speed devices. Symmetric MOSFET with LDD structure could not mitigate the short channel effects, as the device was scaled down to deep sub-micrometer regime. Asymmetric MOSFET design styles were thus adopted to achieve increased device speed. In this paper, two asymmetric MOSFETs are designed and simulated using device simulator (SILVACO) -one with LDD at drain side only and second with unequal junction depths.Keywords-short channel effects, lightly doped drain (LDD), Si-SiO 2 interface, hot electron effects, impact ionization.

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Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

Cited by 58 publications

References 13 publications

Verify and Extend VLSI Device Models

Verify and Extend VLSI Device Models

Scrutiny of Leakage Currents with Insulating Materials for Transistor Applications

Design styles of Asymmetric nMOS and their Simulation

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