Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications

Shukla, Satyam; Ray, Kailash Chandra

doi:10.1109/ises47678.2019.00042

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…While the hardness of commercial ICs has generally improved considering hard errors, the technological changes resulted in more susceptibility to transient radiation effects, thus requiring more attention to faults caused by SEE [16]. Among SEEs, we can distinguish Single-Event Transient (SET) that model the transitory variation of a combinatory output and Single-Event Upset (SEU) that represents the toggle (or bit-flip) of a memory element state when a SEE occurs [6,11,16].…”

Section: Related Workmentioning

confidence: 99%

“…This is no longer just a concern for space applications, as even commercially used nanoscale circuits at sea level have become more susceptible to particles present in the atmosphere [1][2][3][4]. The widespread presence of ICs in various fields, including aerospace, military, medical systems, and even household appliances, such as Internet of Things (IoT) systems, makes fault-tolerant techniques increasingly important for space and terrestrial applications [5][6][7]. Finding efficient methods for evaluating these techniques to meet this demand is essential.…”

Section: Introductionmentioning

confidence: 99%

“…Finding efficient methods for evaluating these techniques to meet this demand is essential. It is crucial to enable this evaluation early in the IC design process in order to minimize the budget spent on expensive particle accelerator facilities [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

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A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

et al. 2023

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The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

et al. 2023

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“…To improve the performance with low-overhead, selective TMR approach can be used. The selective TMR approach provides the fault-tolerance capability to frequently used blocks such as arithmetic logic units (ALUs) [17], register files [14], even only multipliers [18]. However, the fault tolerance capability in the selective TMR approach is less compared to the conventional TMR approach [19].…”

Section: Introductionmentioning

confidence: 99%

A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

Shukla

Ray

2022

IEEE Access

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Radiation can affect the correct behavior of an electronic device. Hence, the microprocessors used for space missions need to be protected against fault. TMR (Triple modular redundancy) is used for mitigating various kinds of faults in an electronic circuit. Although TMR provides an excellent level of reliability, it takes a large area and suffers from high power consumption. To reduce the area and power overheads DMR (double modular redundancy) is used. The DMR approach significantly reduces the resource overhead but it also reduces the performance by imposing timing penalty. Various methods have been proposed since the incarnation of TMR and DMR, but the resource overhead is still a challenging issue. Hence, in this work, a new DMR based reconfigurable quad-core RV32IM processor architecture is proposed for fault-tolerant applications. Depending upon the environment of operation and application sensitivity, the designed processor can be reconfigured to work either in normal mode or fault-tolerant mode. The novelty of the proposed architecture is that the reconfigurable feature reduces the resource overhead and makes the processor energy-efficient by optimally using all four processor cores to provide fault-tolerant results. The proposed computing architecture is designed using Verilog HDL(Hardware Description Language) and synthesized on 32nm CMOS (Complementary Metal-Oxide Semiconductor) process technology node using Synopsys Design Compiler EDA (Electronic Design Automation) tool. Compared to unprotected design, the synthesis tool reports -21.75% reduction in power with a time penalty of +9.96% and area overhead of +17.89% for the proposed fault-tolerant approach. Compared to the state-of-the-art faulttolerant computing system, the proposed design achieves -2.26% low area overhead with its reliability intact as DMR. Further, the proposed processor is prototyped and tested on FPGA (field-programmable gate array) with fault-injection using SEM (soft error mitigation) IP core.INDEX TERMS Reconfigurable VLSI architectures, fault-tolerant processor, FPGA implementation, RISC-V ISA, single event upset.

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FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems

Abdi

Shahoveisi

2022

J Supercomput

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Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications

Cited by 5 publications

References 6 publications

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems

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