Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

“…Compared to other nonvolatile technologies, ferroelectric random access memory (FeRAM) has been shown to consume the least amount of energy per read or write operation compared to other nonvolatile memory technologies; although, it has a larger cell area [4]. Several developments in nonvolatile processing have been introduced [5]- [7], but practical challenges related to system integration prevent their widespread use while further improvement in save/restore energy and time can still expand the scope of this technology.…”

“…The conventional approach shown in Fig. 4 is based on [5] and [6]. A master latch, slave latch, and pair of ferroelectric capacitor dividers comprise this NVDFF.…”

“…The incremental capacitance on the ferroelectric capacitor 5 nodes is large (roughly 200 fF) compared to the internal node of the sensing latch (roughly 10 fF), so a small voltage difference on the high capacitance nodes FET and FEC is converted to a large voltage difference on the latch nodes. In addition to being self-timed (solving challenge #4), this circuit topology ensures sufficient bias (1.1 V) across the fecap before its data is captured (solving challenge #1).…”

“…These issues related to avoiding race conditions, sensing fecaps at high voltage bias, and minimizing peak current prevent the adoption of the conventional ferroelectric DFF based on a pair of fecap dividers [5] (challenges #1, #4, #5). Additionally, Table. IV shows that the proposed NVDFF consumes 40% less energy (from simulation) because it contains 2 fecaps instead of 4.…”

A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

“…To minimize the energy consumption in transceivers, the calibration sequence should be accelerated by providing the predetermined calibration data from a nonvolatile memory (NV-M). The primary requirements for this NV-M are 1) manufacturability by a standard CMOS technology with minimum additional process overheads, 2) in-field multipletime programmability (MTP) and data select-ability to accommodate to multiband/multimode operations, and 3) a self-operated instant-restore function, such as a nonvolatile flip-flop [3], to eliminate the control sequence by a microcontroller.…”