Design and Applications of Approximate Circuits by Gate-Level Pruning

Schlachter, Jérémy; Camus, Vincent; Palem, Krishna V.; Enz, Christian

doi:10.1109/tvlsi.2017.2657799

Cited by 76 publications

(67 citation statements)

References 24 publications

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“…[36] accommodates voltage scaling in arithmetic units for saving energy by disabling some of the input bits. Another scheme proposed in [37] prune the bitwidth of all the input operands in simple data-paths, enabling power savings due to the reduced switching activity. Although very interesting, such works overlook the impact of precision scaling on the reduction of the path-delay; and did not consider 'when and where' they need to apply it in pipelined datapaths as we do.…”

Section: Related Workmentioning

confidence: 99%

Significance-Driven Data Truncation for Preventing Timing Failures

Tsiokanos

Mukhanov

Nikolopoulos

et al. 2019

IEEE Trans. Device Mater. Relib.

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The continuous scaling of transistor sizes and the increased parametric variations render nanometer circuits more prone to timing failures. To protect circuits from such failures, typically designers adopt pessimistic timing margins, which are estimated under rare worst-case conditions. In this paper, we present a technique that mitigates such pessimistic margins by minimizing the number of timing failures. In particular, we propose a method that minimizes the number of long latency paths within each processor pipeline stage and constraints them in as few stages as possible. Such a method allows us not only to reduce the timing failures, but also to limit the potential errorprone locations to only few pipeline stages. To further reduce these failures, we exploit the path excitation dependence on data patterns and truncate the bitwidth of the operands in the few remaining long latency paths by setting a number of less significant bits (LSBs) to a constant value of zero. Such a truncation may incur quality loss, but this is limited since it is applied only to the LSBs of the few operands that may activate the confined error-prone long latency paths. To evaluate the efficiency of our method, we perform post-place and route dynamic timing analysis based on real operands extracted from a variety of applications. This helps to estimate the bit error rate, while considering the data dependent path excitation. When applied to an IEEE-754 compatible double precision Floating Point Unit (FPU), the proposed approach reduces the timing failures by 216.25× on average compared to the reference FPU design under an assumed 8.1% variation-induced worst-case path delay increase in a 45 nm process. Our results show that the path shaping alone introduces a negligible 0.25% area and 5.7% power overheads with no performance cost. Finally, we demonstrate that by combining the path shaping with aggressive operand bitwidth truncation, we enable power savings of up-to 44.7% due to the substantially reduced switching activity at minimal quality loss.

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Section: Related Workmentioning

confidence: 99%

Significance-Driven Data Truncation for Preventing Timing Failures

Tsiokanos

Mukhanov

Nikolopoulos

et al. 2019

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

show abstract

“…Recent schemes use precision scaling to reduce the energy consumption [8], while authors in [9] use it for mitigating the estimated delay increase over few years. Other approximate based schemes [10], [11], [12] truncate the bitwidth of all the input operands in simple data-paths, enabling power savings due to the reduced switching activity, while compromising accuracy. The common idea behind all the existing schemes lies on the static estimation of the potential delay increase under scaled voltage or variations and the reduction of the precision in arithmetic instructions at design time.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Tsiokanos

Mukhanov

Karakonstantis

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…This is a popular method because of its simplicity, but the work risks being applicable only to the tested application. Examples of such works [23,24] have utilized approximate multipliers and adders in image processing scenarios. The error metric then is measured on the test data (input images) and how well the approximate circuits formed the image as opposed to the ideal situation.…”

Section: Related Workmentioning

confidence: 99%

Error metrics determination in functionally approximated circuits using SAT solvers

2020

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Approximate computing is an emerging design paradigm that offers trade-offs between output accuracy and computation efforts by exploiting some applications' intrinsic error resiliency. Computation of error metrics is of paramount importance in approximate circuits to measure the degree of approximation. Most of the existing techniques for evaluating error metrics apply simulations which may not be effective for evaluation of large complex designs because of an immense increase in simulation runtime and a decrease in accuracy. To address these deficiencies, we present a novel methodology that employs SAT (Boolean satisfiability) solvers for fast and accurate determination of error metrics specifically for the calculation of an average-case error and the maximum error rate in functionally approximated circuits. The proposed approach identifies the set of all errors producing assignments to gauge the quality of approximate circuits for real-life applications. Additionally, the proposed approach provides a test generation method to facilitate design choices, and acts as an important guide to debug the approximate circuits to discover and locate the errors. The effectiveness of the approach is demonstrated by evaluating the error metrics of several benchmark-approximated adders of different sizes. Experimental results on benchmark circuits show that the proposed SAT-based methodology accurately determines the maximum error rate and an average-case error within acceptable CPU execution time in one go, and further provides a log of error-generating input assignments. OPEN ACCESSCitation: Abed S, Behiry AAMR, Ahmad I (2020) Error metrics determination in functionally approximated circuits using SAT solvers. PLoS ONE 15(1): e0227745. https://doi.org/10.

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Design and Applications of Approximate Circuits by Gate-Level Pruning

Cited by 76 publications

References 24 publications

Significance-Driven Data Truncation for Preventing Timing Failures

Significance-Driven Data Truncation for Preventing Timing Failures

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Error metrics determination in functionally approximated circuits using SAT solvers

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