Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

Dadoria, Ajay Kumar; Khare, Kavita

doi:10.1007/s00034-019-01059-4

Cited by 11 publications

(4 citation statements)

References 22 publications

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“…Average power consumption, circuit delays, power delay products (PDP), energy consumption, and energy delay products (EDP) [44] of the proposed circuit are compared with the reference adiabatic circuits shown in section 2. The comparisons are performed with the HP-PTM at 45 nm and 16 nm, respectively [45].…”

Section: Resultsmentioning

confidence: 99%

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Vanlalchaka

Maity

2023

Eng. Res. Express

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Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3µm CMOS technology, with channel length and width set at 0.3µm and 0.75µm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively

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Section: Resultsmentioning

confidence: 99%

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Vanlalchaka

Maity

2023

Eng. Res. Express

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“…From the simulation results ION and IOFF currents were calculated for 3σ deviation of 10% from the standard values for different parameters like LTube, WTube, HTube, TTube, Small deviations on WFF have high impact on electrical behaviour of CNTFET devices. After calculating the mean (µ) and standard deviation (σ), we normalize the standard deviation by dividing with mean ( 𝜎 µ ⁄ ) for checking the variability of the different device parameters [5,18].…”

Section: Interconnectsmentioning

confidence: 99%

“…CNT are broadly classified as single-walled (SWCNT) or multi-walled (MWCNT). For single-walled (SWCNT) the devices dimensions are less than 1 nm and MWCNT are prepared by connecting various tubes of CNT in which the device dimension greater than 100 nm are attainable [5,6]. The 3-D structure of CNTFET is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Dadoria

Garg²,

Kushwah³

et al. 2021

Preprint

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With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.

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“…The continuous reduction in device size leads to exponential increase in the leakage power due to Short Channel Effects. At the device level several alternative structures like CNTFET [9], FinFET and TFET [10] are proposed in place of conventional MOSFET. The use of FinFET as an alternative to CMOS further improves the energy recovery of the adiabatic logic.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Adiabatic Vedic Multipliers

Kaza¹

2021

TURCOMAT

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Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

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Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

Cited by 11 publications

References 22 publications

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Performance Analysis of Adiabatic Vedic Multipliers

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