Design and Analysis of High-Throughput Two-Cycle Multiply-Accumulate (MAC) Architectures for Fixed-Point Arithmetic

Bhadra, Arijit; Samui, Suman

doi:10.1109/calcon56258.2022.10059958

2022 IEEE Calcutta Conference (CALCON) 2022

DOI: 10.1109/calcon56258.2022.10059958

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Design and Analysis of High-Throughput Two-Cycle Multiply-Accumulate (MAC) Architectures for Fixed-Point Arithmetic

Arijit Bhadra

Suman Samui

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Design and Analysis of High-Throughput Two-Cycle Multiply-Accumulate (MAC) Architectures for Fixed-Point Arithmetic

Cited by 1 publication

References 16 publications

VLSI Architecture of High Throughput Processing Unit for Efficiently Executing 2D Convolution for Deep Neural Network based Applications

VLSI Architecture of High Throughput Processing Unit for Efficiently Executing 2D Convolution for Deep Neural Network based Applications

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