VLSI Architecture of High Throughput Processing Unit for Efficiently Executing 2D Convolution for Deep Neural Network based Applications

Gari, Bhanuprakash Reddy Peddasubbanna; Samui, Suman; Garai, Soumen

doi:10.1109/codec60112.2023.10465738

2023 8th International Conference on Computers and Devices for Communication (CODEC) 2023

DOI: 10.1109/codec60112.2023.10465738

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VLSI Architecture of High Throughput Processing Unit for Efficiently Executing 2D Convolution for Deep Neural Network based Applications

Bhanuprakash Reddy Peddasubbanna Gari,

Suman Samui,

Soumen Garai

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VLSI Architecture of High Throughput Processing Unit for Efficiently Executing 2D Convolution for Deep Neural Network based Applications

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