Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO₂/Al₂O₃Gate-Stack

Abstract

High performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm 2 /V.s, and a peak field effect mobility of 154 cm 2 /V.s, in 2 µm gate length MOSFETs. The gate stack was designed to minimise interface states and comprised a 0.7 nm thermally grown SiO2 on 4H-SiC, followed by Al2O3 and a metal gate contact. In this way carbon remaining following SiC oxidation is significantly reduced. A density of interface traps in the range 6×10 11-5×10 10 cm-2 eV-1 is also obtained. Temperature dependent electrical data reveals that the high mobility results from conduction being phonon-limited rather than Coulomb-limited. Furthermore, universal mobility in these 4H-SiC MOSFETs is shown to be up to 50% of that observed in Si devices. Expressions for electric field dependent contributions to mobility are presented. A steep sub-threshold slope of 127 mV/dec indicates low electrical defect density. A temperature coefficient of-4.6 mV/K in threshold voltage is similar to that in Si MOSFETs.

Low Temperature Hydrophilic SiC Wafer Level Direct Bonding for Ultrahigh-Voltage Device Applications

“…Since the epitaxy growth is less compact than the SiC substrate, Si atom is much easier to sputter during activation. Therefore, more activated C atoms could form a graphite-like structure at the surface, which leads to an aforementioned relative lower CA and higher RMS roughness [25][26][27].…”

Electrical characterization of near-interface traps in thermally oxidized and NO-annealed SiO2/4H-SiC metal-oxide-semiconductor capacitors

“…The ability of NO annealing to improve the quality of the thermally oxidized SiO 2 /4 H-SiC-based MOS structure is consistent with many previous reports. The microscopic origin behind this phenomenon has been ascribed to the decreased concentration of both interface traps and NITs [30], either physically or through chemical passivation of carbon-related defects that form complex clusters involving C, O or Si, which exist in a number of charge states [31,32], and the formation of strong Si ≡ N bonds that passivate silicon-related traps originating from dangling and strained bonds [33,34]. Although the defect content was decreased by NO annealing, similar interface traps and NITs existed in both samples.…”

Fully controllable silicon nanowire fabricated using optical lithography and orientation dependent oxidation

“…The interface traps could be another reason for the high S. The trap density of ALD Al 2 O 3 on silicon is an order of magnitude higher than the high-quality thermal oxide [55,56]. The interface traps can be reduced by using high quality thermal oxide or inserting a thin layer of thermally grown oxide between NWs and Al 2 O 3 [57]. Subthreshold swing can also be largely reduced by controlling the NWs channel using gate-all-around (GAA) with thin gate oxide.…”