Design and analysis of gray code generator as test pattern generator

Narasimha, Palla; Krishna, Maddala Vamsi; Somanathan, Geethu Remadevi; Bhakthavatchalu, Ramesh

doi:10.1109/icces51350.2021.9489251

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Gray Code Pointer Design1

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2022

2023

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Cited by 2 publications

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“…Gray code is an error minimization reliability code, which can greatly reduce the error caused by the circuit when changing from one state to the next. This encoding method only has one bit variation between two adjacent codes [8]. The disadvantage is that Gray codes are unauthorised codes, which cannot be directly used for calculation and comparison, and need to be converted into binary codes for calculation [9].…”

Section: Gray Code Pointer Designmentioning

confidence: 99%

Design and optimization of asynchronous FIFO based on Verilog HDL

Cheng

2023

Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022)

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SoC system is a new chip design scheme, which can integrate a large number of functions in the same chip, so it has high requirements for asynchronous data transmission between different modules. Asynchronous FIFO is an efficient and reliable data transmission mode, which is often used as a data matcher in SoC system. This paper, through the modular design, layer by layer construction method, designs a asynchronous FIFO, and for the common problems to optimize, makes its performance more reliable. And according to the simulation results, it can be judged that this design can effectively and reliably carry out asynchronous data transmission.

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Section: Gray Code Pointer Designmentioning

confidence: 99%